![](http://datasheet.mmic.net.cn/330000/PCI4410A_datasheet_16443872/PCI4410A_36.png)
2
–
20
Table 2
–
15. CardBus PC Card Interface Control Terminals
TERMINAL
NAME
NUMBER
PDV
I/O
DESCRIPTION
GHK
CAUDIO
182
C10
I
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI4410A
device supports the binary audio mode and outputs a binary signal from the card to SPKROUT.
CBLOCK
151
E19
I/O
CardBus lock. CBLOCK is used to gain exclusive access to a target.
CCD1
CCD2
123
185
L19
A9
I
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and
CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type.
CDEVSEL
155
E17
I/O
CardBus device select. The PCI4410A device asserts CDEVSEL to claim a CardBus cycle as the
target device. As a CardBus initiator on the bus, the PCI4410A device monitors CDEVSEL until a target
responds. If no target responds before timeout occurs, the PCI4410A device terminates the cycle with
an initiator abort.
CFRAME
159
E14
I/O
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted
to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted.
When CFRAME is deasserted, the CardBus bus transaction is in the final data phase.
CGNT
154
F15
O
CardBus bus grant. CGNT is driven by the PCI4410A device to grant a CardBus PC Card access to
the CardBus bus after the current data transaction has been completed.
CINT
180
A10
I
CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the
host.
CIRDY
158
C15
I/O
CardBus initiator ready. CIRDY indicates the CardBus initiator
’
s ability to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and
CTRDY are asserted. Until both CIRDY and CTRDY are sampled asserted, wait states are inserted.
CPERR
152
F14
I/O
CardBus parity error. CPERR reports parity errors during CardBus transactions, except during special
cycles. It is driven low by a target two clocks following that data when a parity error is detected.
CREQ
171
E12
I
CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus
bus as an initiator.
CSERR
181
B10
I
CardBus system error. CSERR reports address parity errors and other system errors that could lead
to catastrophic results. CSERR is driven by the card synchronous to CCLK, but deasserted by a weak
pullup, and may take several CCLK periods. The PCI4410A device can report CSERR to the system
by assertion of SERR on the PCI interface.
CSTOP
153
E18
I/O
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus
transaction. CSTOP is used for target disconnects, and is commonly asserted by target devices that
do not support burst data transfers.
CSTSCHG
183
E10
I
CardBus status change. CSTSCHG alerts the system to a change in the card
’
s status, and is used as
a wake-up mechanism.
CTRDY
157
A16
I/O
CardBus target ready. CTRDY indicates the CardBus target
’
s ability to complete the current data phase
of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and CTRDY
are asserted; until this time, wait states are inserted.
CVS1
CVS2
179
165
F11
E13
I/O
CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with
CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and
card type.