![](http://datasheet.mmic.net.cn/330000/PCI4410A_datasheet_16443872/PCI4410A_40.png)
3
–
2
Tied for Open Drain
OE
Pad
VCCP
Figure 3
–
2. 3-State Bidirectional Buffer
NOTE:
Unused pins (input or I/O) must be held high or low to prevent them from floating.
3.3
Clamping Voltages
The clamping voltages are set to match whatever external environment the PCI4410A device is interfaced with: 3.3 V
or 5 V. The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from external
signals. The core power supply always is 3.3 V and is independent of the clamping voltages. For example, PCI
signaling can be either 3.3 V or 5 V, and the PCI4410A device must reliably accommodate both voltage levels. This
is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a
system designer desires a 5-V PCI bus, V
CCP
can be connected to a 5-V power supply.
The PCI4410A device requires four separate clamping voltages because it supports a wide range of features. The
four voltages are listed and defined in Section 10.2,
Recommended Operating Conditions
.
3.4
Peripheral Component Interconnect (PCI) Interface
The PCI4410A device is fully compliant with the
PCI Local Bus Specification
. The PCI4410A device provides all
required signals for PCI master or slave operation, and can operate in either a 5-V or 3.3-V signaling environment
by connecting the V
CCP
terminals to the desired voltage level. In addition to the mandatory PCI signals, the PCI4410A
device provides the optional interrupt signal INTA.
3.4.1
PCI Bus Lock (LOCK)
The bus-locking protocol defined in the
PCI Local Bus Specification
is not highly recommended, but is provided on
the PCI4410A device as an additional compatibility feature. The PCI LOCK signal can be routed to the MFUNC4
terminal via the multifunction routing register. See Section 4.32,
Multifunction Routing Register
,
for details. Note that
the use of LOCK is supported only by PCI-to-CardBus bridges in the downstream direction (away from the processor).
PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted,
nonexclusive transactions can proceed to an address that currently is not locked. A grant to start a transaction on
the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible
for different initiators to use the PCI bus while a single master retains ownership of LOCK. Note that the CardBus
signal for this protocol is CBLOCK to avoid confusion with the bus clock.
An agent may need to do an exclusive operation because a critical access to memory might be broken into several
transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by
PCI to be 16 bytes, aligned. The LOCK protocol defined by the
PCI Local Bus Specification
allows a resource lock
without interfering with nonexclusive real-time data transfer, such as video.
The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario,
the arbiter will not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A complete
bus lock may have a significant impact on the performance of the video. The arbiter that supports complete bus lock
must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation
is in progress.
The PCI4410A device supports all LOCK protocol associated with PCI-to-PCI bridges, as also defined for
PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve