- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367854 > PDI1394L41 (NXP Semiconductors N.V.) Content Protection AV Link Layer(內(nèi)容可保護(hù)的AV鏈接層控制器) PDF資料下載
參數(shù)資料
| 型號： | PDI1394L41 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Content Protection AV Link Layer(內(nèi)容可保護(hù)的AV鏈接層控制器) |
| 中文描述： | 影音內(nèi)容保護(hù)鏈路層（內(nèi)容可保護(hù)的視聽鏈接層控制器） |
| 文件頁數(shù)： | 49/81頁 |
| 文件大小： | 303K |
| 代理商： | PDI1394L41 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁當(dāng)前第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁
Philips Semiconductors
Preliminary specification
PDI1394L41
1394 content protection AV link layer controller
2000 Apr 15
46
13.1
Link Control Registers
13.1.1
ID Register (IDREG) – Base Address: 0x000
The ID register is automatically updated by the attached PHY with the proper Node ID after completion of the bus reset.
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
SV00915
NODE ID
BUS ID
VERSION CODE
3130
PART CODE
Reset Value 0xFFFF1001
Bit 31..22:
R/W
BUS ID: The 10-bit bus number that is used with the Node ID in the source address for outgoing packets and used to
accept or reject incoming packets. This field reverts to all ‘1’s (0x3FF) upon bus reset.
NODE ID: Used in conjunction with Bus ID in the source address for outgoing packets and used to accept or reject
incoming packets. This register auto-updates with the node ID assigned after the 1394 bus Tree-ID sequence.
PART CODE: “02” designates PDI1394L41.
VERSION CODE: “01” shows this is revision level 1 of this part.
Bit 21..16:
R/W
Bit 15..8:
Bit 7..0:
R
R
13.1.2
The General Link control register is used to program the Link Layer isochronous transceiver, as well as the overall link transceiver. It also
provides general link status.
General Link Control (LNKCTL) – Base Address: 0x004
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
6
5 4 3
2 1
0
SV00892
I
R
R
B
C
S
C
C
R
R
T
R
BSYCTRL
ATACK
31 30
T
R
D
L
Reset Value 0x46000002
Bit 31:
R/W
IDValid (IDVALID): When equal to one, the PDI1394L41 accepts the packets addressed to this node. This bit is
automatically set after selfID complete and node ID is updated.
Receive Self ID (RCVSELFID): When asserted, the self-identification packets, generated by each PHY device on the
bus, during bus initialization are received and placed into the asynchronous request queue as a single packet. Bit 30
also enables the reception of PHY configuration packets in the asynchronous request queue.
Busy Control (BSYCTRL): These bits control what busy status the chip returns to incoming packets. The field is
defined below:
000 =
use protocol requested by received packet (either dual phase or single phase)
001 =
RESERVED
010 =
RESERVED
011 =
use single phase retry protocol
100 =
use protocol requested in packet, always send a busy ack (for all packets)
101 =
RESERVED
110 =
RESERVED
111 =
use single phase retry protocol, always send a busy ack
Transmitter Enable (TxENABLE): When this bit is set, the link layer transmitter will arbitrate and send packets.
Receiver Enable (RxENABLE): When this bit is set, the link layer receiver will receive and respond to bus packets.
Data Invariant (DATAINV) refers to the byte ordering of data being presented to the Link through the host interface
(HIF) port and the handling of the address and data lines by the link chip. When DATAINV = 0, the Link is in address
invariant mode. When DATAINV = 1, the Link is in data invariant mode. This bit is only important if the LTLEND
(Little Endian) bit is set (1), otherwise it is ignored. Interpretation of address and data information varies with the
settings of these bits and with the data format being presented. See the section on Big and Little Endian Modes for
more information (Section 12.5.3).
Bit 30:
R/W
Bit 29..27:
R/W
Bit 26:
Bit 25:
Bit 23:
R/W
R/W
R
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDI1394P21 | 3-port Physical Layer Interface(三端口物理層接口) |
| PDI1394P22 | 3-port Physical Layer Interface(三端口物理層接口) |
| PDI1394P24 | 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口) |
| PDI40C1D00 | |
| PDI40C1300 | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDI1394L41BE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 content protection AV link layer controller |
| PDI1394P11 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface |
| PDI1394P11A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface |
| PDI1394P11ABD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface |
| PDI1394P11ABD-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Transceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。