參數(shù)資料
型號(hào): PDI1394L41
廠商: NXP Semiconductors N.V.
英文描述: Content Protection AV Link Layer(內(nèi)容可保護(hù)的AV鏈接層控制器)
中文描述: 影音內(nèi)容保護(hù)鏈路層(內(nèi)容可保護(hù)的視聽鏈接層控制器)
文件頁數(shù): 64/81頁
文件大?。?/td> 303K
代理商: PDI1394L41
Philips Semiconductors
Preliminary specification
PDI1394L41
1394 content protection AV link layer controller
2000 Apr 15
61
13.3
Asynchronous Control and Status Interface
13.3.1
Asynchronous RX/TX Control (ASYCTL) – Base Address: 0x080
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
D
A
A
A
SV00889
MAXRC
TOS
TOF
3130
Reset Value 0x00300320
Bit 23:
Bit 22:
Bit 21:
R/W
R/W
R/W
DIS_BCAST: Disable the reception of broadcast packets (async packets address to 0x3F).
ARXRST: Asynchronous receiver reset. This bit will auto clear when the link layer state machine is idle.
ATXRST: Asynchronous transmitter reset. the power-up reset value of this bit is “0”, however, after every bus reset
this bit is set (1). this effectively disables the asynchronous transmitter; re-enable the async transmitter by clearing
this bit after each bus reset, especially if asynchronous transmission is to be used.
ARXALL: Receive and filter only RESPONSE packets. When set (1), all responses are stored. When clear (0), only
solicited responses are stored.
MAXRC: Maximum number of asynchronous transmitter single phase retries
TOS: Time out seconds, integer of 1 second
TOF: Time out fractions, integer of 1/8000 second. Resets to 0320h, which is 100 milliseconds.
Bit 20:
R/W
Bit 19..16:
Bit 15..13:
Bit 12..0:
R/W
R/W
R/W
13.3.2
Asynchronous RX/TX Memory Status (ASYMEM) – Base Address: 0x084
T
R
T
T
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
T
T
R
R
R
R
R
R
T
R
T
T
T
3130
SV00918
T
Reset Value 0x00033333
Unused bits read ‘0’. The information in this register is primarily used for diagnostics.
TRSPQIDLE: Transmitter response queue is idle. Indicates that the transfer register for this queue is empty.
TREQQIDLE: Transmitter request queue is idle. Indicates that the transfer register for this queue is empty.
RRSPQF: Receiver response queue full.
RRSPQAF: Receiver response queue almost full (precisely 1 more quadlet available).
RRSPQ5AV: Receiver response queue at least 5 quadlets available.
RRSPQE: Receiver response queue empty.
RREQQF: Receiver request queue full.
RREQQAF: Receiver request queue almost full (precisely 1 more quadlet available).
RREQQ5AV: Receiver request queue at least 5 quadlets available.
RREQQE: Receiver request queue empty.
TRSPQF: Transmitter response queue full.
TRSPQAF: Transmitter response queue almost full (precisely 1 more quadlet available).
TRSPQ5AV: Transmitter response queue at least 5 quadlets available.
TRSPQE: Transmitter response queue empty.
TREQQF: Transmitter request queue full.
TREQQAF: Transmitter request queue almost full (precisely 1 more quadlet available).
TREQQ5AV: Transmitter request queue at least 5 quadlets available.
TREQQE: Transmitter request queue empty.
Bit 17:
Bit 16:
Bit 15:
Bit 14:
Bit 13:
Bit 12:
Bit 11:
Bit 10:
Bit 9:
Bit 8:
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
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