參數(shù)資料
型號(hào): PDI1394L41
廠商: NXP Semiconductors N.V.
英文描述: Content Protection AV Link Layer(內(nèi)容可保護(hù)的AV鏈接層控制器)
中文描述: 影音內(nèi)容保護(hù)鏈路層(內(nèi)容可保護(hù)的視聽(tīng)鏈接層控制器)
文件頁(yè)數(shù): 74/81頁(yè)
文件大?。?/td> 303K
代理商: PDI1394L41
Philips Semiconductors
Preliminary specification
PDI1394L41
1394 content protection AV link layer controller
2000 Apr 15
71
15.0
GND = 0V, C
L
= 50pF
AC CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
WAVEFORMS
T
amb
= 0
°
C to +70
°
C
MIN
UNIT
TYP
MAX
t
(parallel
mode)
AV clock period
Figure 36
41.67
ns
t
SU
t
IH
t
OD
AV clock setup time
Figure 36
20
ns
AV clock input hold time
Figure 36
3
ns
AV clock output delay time
Figure 36
3
24
ns
t
WHIGH
t
WLOW
t
PWFS
t
SUP
t
HP
t
SCLKPER
t
DP
t
AS
t
AH
t
CL
t
CH
t
RP
t
ACC
t
DH
t
DS
t
DZ
t
WRP
t
WAIT
t
WWAIT
t
CWH
t
CWL
t
CP
t
CD
t
RESET
t
PWALE
AV clock pulse width HIGH
Figure 36
10
AV clock pulse width LOW
Figure 36
10
AVxFSYNC pulse width HIGH
Figure 37
200
300
ns
PHY-link setup time
Figure 38
6.0
ns
PHY-link hold time
Figure 38
0
ns
SCLK period
Figure 38
20.343
20.345
20.347
ns
PHY-link output delay
Note: C
L
= 20pF
Figure 39
2.0
10.0
ns
Host address setup time
Figure 40
0
ns
Host address hold time
Figure 40
0
ns
Host chip select pulse width LOW
Figure 40
115
ns
Host chip select pulse width HIGH
Figure 40
42
ns
Host read pulse width
Figure 40
115
ns
Host access time
Figure 40
115
ns
Host data hold time
Figure 40
0
ns
Host data setup time
Figure 40
0
ns
Host data bus release (Hi-Z)
Figure 40
15
ns
Host write pulse width
Figure 40
115
ns
WAIT output delay
Figure 40
10
ns
WAIT pulse width
Figure 40
20
ns
CYCLEIN HIGH pulse width
Figure 41
200
ns
CYCLEIN LOW pulse width
Figure 41
200
ns
CYCLEIN cycle period
Figure 41
125
μ
s
CYCLEOUT cycle delay
Figure 42
20
ns
RESET_N pulse width LOW
Figure 43
10
μ
s
ALE pulse width
Figures 7, 8, 9, 10
20
ns
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