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| 型號(hào)： | PEB2245N |
| 廠商： | SIEMENS AG |
| 英文描述： | ?Multipoint Switching and Conferencing Unit - Attenuation? |
| 中文描述： | ？多點(diǎn)交換和會(huì)議股-衰減？ |
| 文件頁(yè)數(shù)： | 11/70頁(yè) |
| 文件大?。?/td> | 1021K |
| 代理商： | PEB2245N |
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PEB 2245
Semiconductor Group
11
Pin Definitions and Functions
(cont’d)
Pin No.
Symbol
Input (I)
Output (O)
Function
24
RD
I
Read:
This signal indicates a read operation and is
internally sampled only if CS is active. The MUSAC puts
data from the selected internal register on the data bus
with the falling edge of RD. RD is active low (Siemens/
Intel bus mode).
DS
I
Data Strobe:
The rising edge marks the end of a valid
read or write operation (Motorola bus mode).
25
WR
I
Write:
This signal initiates a write operation. The WR
input is internally sampled only if CS is active. In this
case the MUSAC loads an internal register with data
from the data bus at the rising edge of WR. WR is active
low (Siemens/Intel bus mode).
Read/Write:
When “high”, identifies a valid
μ
P access as
a read operation. When “l(fā)ow”, identifies a valid
μ
P
access as a write operation (Motorola bus mode).
Address Latch Enable:
In the Intel type multiplexed
μ
P-
interface mode a logical high on this line indicates an
address of an MUSAC internal register on the external
address/data bus. In the Intel type demultiplexed
μ
P-
interface mode this line is hardwired to
V
SS
, in the
demultiplexed Motorola type
μ
P-interface mode it should
be connected to
V
DD
.
Address Data Bus:
If the multiplexed address/data
μ
P-
interface bus mode is selected these pins transfer data
and addresses between the
μ
P and the MUSAC.
R/W
I
2
ALE
I
26
27
29
30
31
32
33
34
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
If a demultiplexed mode is used, these bits interface with
the system data bus.
35
36
37
38
40
41
42
43
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
O
O
O
O
O
O
O
O
PCM-Output Port:
Serial data is sent by these lines at
standard CMOS- or TTL levels. These pins can be
tristated.
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