參數(shù)資料
型號: PEB2245N
廠商: SIEMENS AG
英文描述: ?Multipoint Switching and Conferencing Unit - Attenuation?
中文描述: ?多點交換和會議股-衰減?
文件頁數(shù): 22/70頁
文件大?。?/td> 1021K
代理商: PEB2245N
PEB 2245
Semiconductor Group
22
Table 2
Possible Input Modes
The PEB 2245 runs with either a 4096- or a 8192-kHz device clock as selected with CFR:CPS. Data
rates and clock frequencies may be combined freely. However, processing 8192-kbit/s data, an
8192-kHz clock must be supplied.
The preparation of the input data according to the selected input mode is made in the input buffer.
It converts the serial data of a time-slot to parallel form.
In standard configuration time-slot 0 begins with the rising edge of the SP pulse as shown in upper
half of
figure 11
denoted CSR:(0000XXXX).
As can be seen there the beginning of a input time-slot is defined such, that the input lines have
settled to a stable value, when the datum is actually sampled.
4096- and 8192-kbit/s data is sampled in the middle of the bit period at the falling edge of the
respective data clock. 2048-kbit/s data is sampled after 3/4 of the according bit period, i.e. with the
rising edge of the 4
th
8192-kHz clock cycle or the falling edge of the 2
nd
4096-kHz clock cycle of the
considered bit period.
In the primary access configuration a different timing scheme may apply to the odd (physical) input
lines. They are affected by the content of the clock shift register (CSR), which can be programmed
via the
μ
P interface (
see paragraph 2.2
).
The clock shift register holds the information, how the frame structure is shifted in the primary
access configuration. Its content defaults to 00
H
after power up and is also set to this value,
whenever the standard configuration is selected.
Input Modes
Type
16
×
×
×
+
2048
kbit/s
Single mode
8
4096
kbit/s
Single mode
4
2
×
8192
4
×
4096
8192
8
×
2048
8
×
2048
kbit/s
Single mode
kbit/s
Mixed mode
+
kbit/s
Mixed mode
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