參數(shù)資料
型號(hào)： PEB2245N
廠商： SIEMENS AG
英文描述： ?Multipoint Switching and Conferencing Unit - Attenuation?
中文描述： ？多點(diǎn)交換和會(huì)議股-衰減？
文件頁(yè)數(shù)： 24/70頁(yè)
文件大小： 1021K
代理商： PEB2245N
PEB 2245
Semiconductor Group
24
The four most significant bits of the clock shift register are of interest for the input lines. They only
affect the odd input lines (
see section Clock Shift Register
): The frame structure can be advanced
by the number of bit periods programmed to the RS2, RS1 and RS0 bits of the CSR. For example,
programming the CSR with (1100XXXX) a new frame starts 6-bit periods before the rising edge of
the SP pulse.
Selecting RRE to logical 1 the frame is delayed by half a bit period (
see figure 11
). The data is then
sampled in the middle of the respective bit period for all data rates.
The last line of
figure 11
shows the sampling instants for the CSR entry (1001XXXX). Then the
input frame is advanced by 4-bit periods and delayed by a half resulting in a 3 1/2 clock period
advancement of the input frame. For further examples refer to
figure 19
.
Thus the frame structure may be selected to begin at any 1/2-bit period value between a resulting
advancement of 7-bit periods and a resulting delay of 1/2 a bit period.
Setting CSR = 0X
H
the same timing conditions apply to even and odd inputs. Then all system
interface inputs are processed in the same way they are in the standard configuration.
Output Buffer
The output buffer rearranges the data read from the speech memory. It basically converts the
parallel data to serial data. Depending on the validity bit the output buffer outputs the data or
switches the line to high impedance. The most significant bits of the 256 words in the connection
memory are interpreted as validity bits for the 256 possible output channels: A logical 0 enables the
programmed connection, a logical 1 tristates the output.
The mode register (MOD) bits MI1, MI0, MO1 and MO0 control this process. The possible output
modes are listed in
table 3
.
Table 3
Possible Output Modes
Figure 12
shows when the single bits are output. In standard configuration they are clocked off at
the rising clock edge at the beginning of the considered bit period. Time-slot 0 starts two
t
CP8
before
the falling edge of the SP pulse.
In primary access configuration the even output lines are affected by the XS2, XS1, XS0 and XFE
entries in the clock shift register. The output frame is synchronized with the rising edge of the SP
signal.
Output Modes
Type
8
×
×
×
+
2048
kbit/s
Single mode
4
4096
kbit/s
Single mode
2
1
×
8192
2
×
4096
8192
4
×
2048
4
×
2048
kbit/s
Single mode
kbit/s
Mixed mode
+
kbit/s
Mixed mode
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參數(shù)描述
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