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PEB 2245
Semiconductor Group
58
The PCM samples of each input channel first pass through an input processing stage. In this stage,
an input attenuation level (0, 3, 6 or 9 dB) and a noise suppression threshold can be programmed
individually for each channel. Following the input processing the PCM data is expanded according
to the A- or
μ
-law encoding rules and written to the Data Memory (DM). Additionally the PCM data
of each input channel is added to the Conference Sum Memory (CSM). The DM location (1 out of
64) is specified by the conference control address (cca) and the CSM location (1 out of 21) is
specified by the conference number when writing to the Conference Control Memory (CCM).
The PCM data then passes through a substractor stage such that the resulting output channel for
a given subscriber contains the contribution of all the other channels in the conference except its
own. Finally the PCM data is forwarded to the output channel after PCM compression and an
optional output attenuation of 3 dB.
The common characteristics of all conferences (encoding law and byte format) as well as the
conferencing function itself are selected in the configuration register CFR.
The input channel and the individual conference parameters of a conference are programmed in the
Conference Control Memory (CCM) which is a 20-bit (data)
×
6-bit (address) memory. The 6-bit
address, also called conference control address (cca), allows a maximum of 64 channels
simultaneously involved in conference applications. The cca can be selected at random i.e. for each
new participant of a conference any still not used cca can be taken.
The 20-bit data field of the Conference Control Memory (CCM) specifies:
– the logical input line and time-slot number (9 bits),
– the input attenuation level (2 bits),
– the output attenuation level (1 bit),
– the noise suppression threshold (2 bits),
– the inversion function (1 bit) and
– the conference number (5 bits).
The output channel and the conference mode are programmed in the Connection Memory (CM)
which is an 11-bit (data)
×
8-bit (address) memory. For each of the 256 output channels the 11-bit
data field specifies the source and characteristics of the output line and time-slot selected by the CM
address. Two cases can be distinguished:
In the transparent switch mode 11 data bits specify:
– the selection of the transparent switching mode (1 bit),
– the output driver state (enabled/tristated) (1 bit) and
– the logical input line and time-slot number (9 bits).
In the conference switching mode 8 data bits (3 bits are not used) specify:
– the selection of the conference switching mode (1 bit),
– the output driver state, enabled or tristated (1 bit) and
– the conference control address cca (6 bits).