- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄1962 > PI7C9X20404SLCFDE (Pericom)IC PCIE PACKET SWITCH 128LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | PI7C9X20404SLCFDE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 10/77頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE PACKET SWITCH 128LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | SlimLine™ |
| 應(yīng)用： | 封裝開(kāi)關(guān)，4 端口/4 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 128-LQFP 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤(pán) |
| 安裝類(lèi)型： | 表面貼裝 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)當(dāng)前第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)
PI7C9X20404SL
4Port-4Lane PCI Express Switch
SlimLine
TM Family
Datasheet
Page 18 of 77
July 2009 – Revision 1.2
Pericom Semiconductor
5.2
DATA LINK LAYER (DLL)
The Data Link Layer (DLL) provides a reliable data transmission between two PCI Express points. An ACK/NACK
protocol is employed to guarantee the integrity of the packets delivered. Each Transaction Layer Packet (TLP) is
protected by a 32-bit LCRC for error detection. The DLL receiver performs LCRC calculation to determine if the
incoming packet is corrupted in the serial link. If an LCRC error is found, the DLL transmitter would issue a NACK
data link layer packet (DLLP) to the opposite end to request a re-transmission, otherwise an ACK DLLP would be
sent out to acknowledge on reception of a good TLP.
In the transmitter, a retry buffer is implemented to store the transmitted TLPs whose corresponding ACK/NACK
DLLP have not been received yet. When an ACK is received, the TLPs with sequence number equals to and smaller
than that carried in the ACK would be flushed out from the buffer. If a NACK is received or no ACK/NACK is
returned from the link partner after the replay timer expires, then a replay mechanism built in DLL transmitter is
triggered to re-transmit the corresponding packet that receives NACK or time-out and any other TLP transmitted
after that packet.
Meanwhile, the DLL is also responsible for the initialization, updating, and monitoring of the flow-control credit.
All of the flow control information is carried by DLLP to the other end of the link. Unlike TLP, DLLP is guarded
by 16-bit CRC to detect if data corruption occurs.
In addition, the Media Access Control (MAC) block, which is consisted of LTSSM, multiple lanes deskew,
scrambler/de-scrambler, clock correction from inserting skip order-set, and PIPE-related control/status circuits, is
implemented to interface physical layer with data link layer.
5.3
TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION)
The receiving end of the transaction layer performs header information retrieval and TC/VC mapping (see section
5.5), and it validates the correctness of the transaction type and format. If the TLP is found to contain illegal header
or the indicated packet length mismatches with the actual packet length, then a Malformed TLP is reported as an
error associated with the receiving port. To ensure end-to-end data integrity, a 32-bit ECRC is checked against the
TLP at the receiver if the digest bit is set in header.
5.4
ROUTING
The transaction layer implements three types of routing protocols: ID-based, address-based, and implicit routing.
For configuration reads, configuration writes, transaction completion, and user-defined messages, the packets are
routed by their destination ID constituted of bus number, device number, and function number. Address routing is
employed to forward I/O or memory transactions to the destination port, which is located within the address range
indicated by the address field carried in the packet header. The packet header indicates the packet types including
memory read, memory write, IO read, IO write, Message Signaling Interrupt (MSI) and user-defined message.
Implicit routing is mainly used to forward system message transactions such as virtual interrupt line, power
management, and so on. The message type embedded in the packet header determines the routing mechanism.
If the incoming packet can not be forwarded to any other port due to a miss to hit the defined address range or
targeted ID, this is considered as Unsupported Request (UR) packet, which is similar to a master abort event in PCI
protocol.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C9X20505GPBNDE | IC PCIE PACKET SWITCH 256BGA |
| PI7C9X20508GPBNDE | IC PCIE PACKET SWITCH 256BGA |
| PI7C9X440SLBFDE | IC PCIE-TO-USB 2.0 CTRLR 128LQFP |
| PI7C9X442SLBFDE | IC PCIE-TO-USB2.0 SWIDGE 128LQFP |
| PI7C9X7952AFDE | IC PCIE-TO-UART BRIDGE 128LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C9X20404SLCFDEX | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20505GPBNDE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 5port 5lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20508GPANDE | 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube |
| PI7C9X20508GPBEVB | 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD - Boxed Product (Development Kits) |
| PI7C9X20508GPBNDE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 5port 8lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。