TM Family Datasheet Page 48 of 77 July 2009 – Rev" />
參數(shù)資料
型號(hào)： PI7C9X20404SLCFDE
廠商： Pericom
文件頁數(shù)： 43/77頁
文件大?。?/td> 0K
描述： IC PCIE PACKET SWITCH 128LQFP
標(biāo)準(zhǔn)包裝： 90
系列： SlimLine™
應(yīng)用： 封裝開關(guān)，4 端口/4 線道
接口： PCI Express
封裝/外殼： 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20404SL
4Port-4Lane PCI Express Switch
SlimLine
TM Family
Datasheet
Page 48 of 77
July 2009 – Revision 1.2
Pericom Semiconductor
15:0
SSVID
RO
It indicates the sub-system vendor id. The default value may be changed by
SMBus or auto-loading from EEPROM.
Reset to 0000h.
7.2.59
SUBSYSTEM ID REGISTER – OFFSET C4h
BIT
FUNCTION
TYPE
DESCRIPTION
31:16
SSID
RO
It indicates the sub-system device id. The default value may be changed by
SMBus or auto-loading from EEPROM.
Reset to 0000h.
7.2.60
GPIO CONTROL REGISTER – OFFSET D8h (Upstream Port Only)
BIT
FUNCTION
TYPE
DESCRIPTION
0
GPIO [0] Input
RO
State of GPIO [0] pin
1
GPIO [0] Output
Enable
RW
0b: GPIO [0] is an input pin
1b: GPIO [0] is an output pin
Reset to 0b.
2
GPIO [0] Output
Register
RW
Value of this bit will be output to GPIO [0] pin if GPIO [0] is configured as
an output pin.
Reset to 0b.
3
Reserved
RO
Reset to 0b.
4
GPIO [1] Input
RO
State of GPIO [1] pin.
5
GPIO [1] Output
Enable
RW
0b: GPIO [1] is an input pin
1b: GPIO [1] is an output pin
Reset to 0b.
6
GPIO [1] Output
Register
RW
Value of this bit will be output to GPIO [1] pin if GPIO [1] is configured as
an output pin.
Reset to 0b.
7
Reserved
RO
Reset to 0b.
8
GPIO [2] Input
RO
State of GPIO [2] pin
9
GPIO [2] Output
Enable
RW
0b: GPIO [2] is an input pin
1b: GPIO [2] is an output pin
Reset to 0b.
10
GPIO [2] Output
Register
RW
Value of this bit will be output to GPIO [2] pin if GPIO [2] is configured as
an output pin.
Reset to 0b.
11
Reserved
RO
Reset to 0b.
12
GPIO [3] Input
RO
State of GPIO [3] pin.
13
GPIO [3] Output
Enable
RW
0b: GPIO [3] is an input pin
1b: GPIO [3] is an output pin
Reset to 0b.
14
GPIO [3] Output
Register
RW
Value of this bit will be output to GPIO [3] pin if GPIO [3] is configured as
an output pin.
Reset to 0b.
15
Reserved
RO
Reset to 0b.
16
GPIO [4] Input
RO
State of GPIO [4] pin.
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