TM Family Datasheet Page 12 of 77 July 2009 – Rev" />
參數(shù)資料
型號(hào)： PI7C9X20404SLCFDE
廠商： Pericom
文件頁(yè)數(shù)： 4/77頁(yè)
文件大?。?/td> 0K
描述： IC PCIE PACKET SWITCH 128LQFP
標(biāo)準(zhǔn)包裝： 90
系列： SlimLine™
應(yīng)用： 封裝開關(guān)，4 端口/4 線道
接口： PCI Express
封裝/外殼： 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20404SL
4Port-4Lane PCI Express Switch
SlimLine
TM Family
Datasheet
Page 12 of 77
July 2009 – Revision 1.2
Pericom Semiconductor
3 PIN DESCRIPTION
3.1
PCI EXPRESS INTERFACE SIGNALS
NAME
PIN
TYPE
DESCRIPTION
REFCLKP
REFCLKN
91
93
I
Reference Clock Input Pairs: Connect to external 100MHz
differential clock.
The input clock signals must be delivered to the clock buffer cell
through an AC-coupled interface so that only the AC information of
the clock is received, converted, and buffered. It is recommended that a
0.1uF be used in the AC-coupling.
PERP [3:0]
120, 104, 87,
70
I
PERN [3:0]
121, 103, 88,
69
I
PCI Express Data Serial Input Pairs: Differential data receive
signals in four ports.
Port 0 (Upstream Port) is PERP[0] and PERN[0]
Port 1 (Downstream Port) is PERP[1] and PERN[1]
Port 2 (Downstream Port) is PERP[2] and PERN[2]
Port 3 (Downstream Port) is PERP[3] and PERN[3]
PETP [3:0]
117, 107, 84,
73
O
PETN [3:0]
116, 108, 83,
74
O
PCI Express Data Serial Output Pairs: Differential data transmit
signals in four ports.
Port 0 (Upstream Port) is PETP[0] and PETN[0]
Port 1 (Downstream Port) is PETP[1] and PETN[1]
Port 2 (Downstream Port) is PETP[2] and PETN[2]
Port 3 (Downstream Port) is PETP[3] and PETN[3]
WAKEUP_L
6
I
Wakeup Signal (Active LOW): When WAKEUP_L is asserted, the
upstream port has to generate a Beacon that is propagated to the Root
Complex/Power Management Controller. Pin has an internal pull-up.
PERST_L
43
I
System Reset (Active LOW): When PERST_L is asserted, the
internal states of whole chip except sticky logics are initialized.
DWNRST_L [3:1]
98, 97, 96
O
Downstream Device Reset (Active LOW): It provides a reset signal
to the devices connected to the downstream ports of Switch. The signal
is active when either PERST_L is asserted or the device is just plugged
into the Switch. DWNRST_L [x] corresponds to Portx, where x= 1,2,3.
3.2
PORT CONFIGURATION SIGNALS
NAME
PIN
TYPE
DESCRIPTION
PRSNT [3:1]
9, 7, 128
I
Present: When asserted low, it represents the device is present in the
slot of downstream ports. Otherwise, it represents the absence of the
device. PRSNT [x] is correspondent to Port x, where x=1,2,3. The pins
have internal pull-down.
SLOTCLK
127
I
Slot Clock Configuration: It determines if the downstream component
uses the same physical reference clock that the platform provides on
the connector. By default, all downstream ports use the same physical
reference clock provided by platform. The pin has internal pull-down.
3.3
MISCELLANEOUS SIGNALS
NAME
PIN
TYPE
DESCRIPTION
EECLK
40
O
EEPROM Clock: Clock signal to the EEPROM interface.
EEPD
41
I/O
EEPROM Data: Bi-directional serial data interface to and from the
EEPROM. The pin is set to 1 by default. The pin has internal pull-up.
SMBCLK
13
I
SMBus Clock: System management Bus Clock. The pin has internal
pull-up.
SMBDATA
16
I/O
SMBus Data: Bi-directional System Management Bus Data. The pin
has internal pull-up.
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PI7C9X20508GPANDE 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube
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