TM Family Datasheet Page 53 of 77 July 2009 – Rev" />
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      • 參數(shù)資料
      型號(hào)： PI7C9X20404SLCFDE
      廠商： Pericom
      文件頁(yè)數(shù)： 49/77頁(yè)
      文件大?。?/td> 0K
      描述： IC PCIE PACKET SWITCH 128LQFP
      標(biāo)準(zhǔn)包裝： 90
      系列： SlimLine™
      應(yīng)用： 封裝開(kāi)關(guān)，4 端口/4 線道
      接口： PCI Express
      封裝/外殼： 128-LQFP 裸露焊盤
      供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
      包裝： 托盤
      安裝類型： 表面貼裝
      PI7C9X20404SL
      4Port-4Lane PCI Express Switch
      SlimLine
      TM Family
      Datasheet
      Page 53 of 77
      July 2009 – Revision 1.2
      Pericom Semiconductor
      BIT
      FUNCTION
      TYPE
      DESCRIPTION
      17
      Non-Fatal Error
      Detected
      RW1C
      Asserted when non-fatal error is detected. Errors are logged in this register
      regardless of whether error reporting is enabled or not in the Device Control
      register.
      Reset to 0b.
      18
      Fatal Error Detected
      RW1C
      Asserted when fatal error is detected. Errors are logged in this register
      regardless of whether error reporting is enabled or not in the Device Control
      register.
      Reset to 0b.
      19
      Unsupported Request
      Detected
      RW1C
      Asserted when unsupported request is detected. Errors are logged in this
      register regardless of whether error reporting is enabled or not in the Device
      Control register.
      Reset to 0b.
      20
      AUX Power
      Detected
      RO
      Asserted when the AUX power is detected by the Switch
      Reset to 1b.
      21
      Transactions Pending
      RO
      Each port of Switch does not issue Non-posted Requests on its own behalf, so
      this bit is hardwired to 0b.
      Reset to 0b.
      31:22
      Reserved
      RO
      Reset to 0.
      7.2.70
      LINK CAPABILITIES REGISTER – OFFSET ECh
      BIT
      FUNCTION
      TYPE
      DESCRIPTION
      3:0
      Maximum Link
      Speed
      RO
      Read as 0001b to indicate the maximum speed of the Express link is 2.5 Gb/s.
      9:4
      Maximum Link
      Width
      RO
      Indicates the maximum width of the given PCIe Link. The width of each port
      is determined by strapped pin or EEPROM pre-loaded value.
      Reset to 000001b (x1) for Port 0.
      Reset to 000001b (x1) for Port 1.
      Reset to 000001b (x1) for Port 2.
      Reset to 000001b (x1) for Port 3.
      11:10
      Active State Power
      Management
      (ASPM) Support
      RO
      Indicates the level of ASPM supported on the given PCIe Link. Each port of
      Switch supports L0s and L1 entry. The default value may be changed by
      SMBus or auto-loading from EEPROM.
      Reset to 01b.
      14:12
      L0s Exit Latency
      RO
      Indicates the L0s exit latency for the given PCIe Link.
      The length of time this port requires to complete transition from L0s to L0 is
      in the range of 256ns to less than 512ns. The default value may be changed
      by SMBus or auto-loading from EEPROM.
      Reset to 011b.
      17:15
      L1 Exit
      Latency
      RO
      Indicates the L1 exit latency for the given PCIe Link.
      The length of time this port requires to complete transition from L1 to L0 is in
      the range of 16us to less than 32us. The default value may be changed by
      SMBus or auto-loading from EEPROM.
      Reset to 000b.
      18
      Reserved
      RO
      Reset to 0b.
      19
      Surprise Down Error
      Reporting Capable
      RO
      For a Downstream port, this bit must be set to 1b if the component supports
      the optional capability of detecting and reporting a Surprise Down error
      condition.
      For Upstream Ports, which does not support this optional capability, this bit
      must be hardwired to 0b.
      Rest to 0b.
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