TM Family Datasheet Page 63 of 77 July 2009 – Rev" />
參數(shù)資料
型號： PI7C9X20404SLCFDE
廠商： Pericom
文件頁數(shù)： 60/77頁
文件大小： 0K
描述： IC PCIE PACKET SWITCH 128LQFP
標準包裝： 90
系列： SlimLine™
應(yīng)用： 封裝開關(guān)，4 端口/4 線道
接口： PCI Express
封裝/外殼： 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20404SL
4Port-4Lane PCI Express Switch
SlimLine
TM Family
Datasheet
Page 63 of 77
July 2009 – Revision 1.2
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
6:4
Low Priority
Extended VC Count
RO
It indicates the number of extended Virtual Channels in addition to the default
VC belonging to the low-priority VC (LPVC) group. The default value may
be changed by SMBus or auto-loading from EEPROM.
Reset to 000b.
7
Reserved
RO
Reset to 0b.
9:8
Reference Clock
RO
It indicates the reference clock for Virtual Channels that support time-based
WRR Port Arbitration. Defined encoding is 00b for 100 ns reference clock.
Reset to 00b.
11:10
Port Arbitration
Table Entry Size
RO
Read as 10b to indicate the size of Port Arbitration table entry in the device is
4 bits.
Reset to 10b.
31:12
Reserved
RO
Reset to 0.
7.2.90
PORT VC CAPABILITY REGISTER 2 – OFFSET 148h (Upstream Only)
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
VC Arbitration
Capability
RO
It indicates the types of VC Arbitration supported by the device for the LPVC
group. This field is valid when LPVC is greater than 0. The Switch supports
Hardware fixed arbitration scheme, e.g., Round Robin and Weight Round
Robin arbitration with 32 phases in LPVC.
Reset to 00000000b.
23:8
Reserved
RO
Reset to 0.
31:24
VC Arbitration Table
Offset
RO
It indicates the location of the VC Arbitration Table as an offset from the base
address of the Virtual Channel Capability register in the unit of DQWD (16
bytes).
Reset to 00h.
7.2.91
PORT VC CONTROL REGISTER – OFFSET 14Ch (Upstream Only)
BIT
FUNCTION
TYPE
DESCRIPTION
0
Load VC Arbitration
Table
RW
When set, the programmed VC Arbitration Table is applied to the hardware.
This bit always returns 0b when read.
Reset to 0b.
3:1
VC Arbitration
Select
RW
This field is used to configure the VC Arbitration by selecting one of the
supported VC Arbitration schemes. The valid values for the schemes
supported by Switch are 0b and 1b. Other value than these written into this
register will be treated as default.
Reset to 0b.
15:4
Reserved
RO
Reset to 0.
7.2.92
PORT VC STATUS REGISTER – OFFSET 14Ch (Upstream Only)
BIT
FUNCTION
TYPE
DESCRIPTION
16
VC Arbitration Table
Status
RO
When set, it indicates that any entry of the VC Arbitration Table is written by
software. This bit is cleared when hardware finishes loading values stored in
the VC Arbitration Table after the bit of “Load VC Arbitration Table” is set.
Reset to 0b.
31:17
Reserved
RO
Reset to 0.
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PI7C9X20505GPBNDE 功能描述:外圍驅(qū)動器與原件 - PCI 5port 5lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20508GPANDE 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube
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PI7C9X20508GPBNDE 功能描述:外圍驅(qū)動器與原件 - PCI 5port 8lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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