TM Family Datasheet Page 40 of 77 July 2009 – Rev" />
參數(shù)資料
型號： PI7C9X20404SLCFDE
廠商： Pericom
文件頁數(shù)： 35/77頁
文件大?。?/td> 0K
描述： IC PCIE PACKET SWITCH 128LQFP
標準包裝： 90
系列： SlimLine™
應用： 封裝開關，4 端口/4 線道
接口： PCI Express
封裝/外殼： 128-LQFP 裸露焊盤
供應商設備封裝： 128-LQFP（14x14）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20404SL
4Port-4Lane PCI Express Switch
SlimLine
TM Family
Datasheet
Page 40 of 77
July 2009 – Revision 1.2
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
23
Fast Back-to-Back
Enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
24
Primary Master
Timeout
RO
Does not apply to PCI Express. Must be hardwired to 0b.
25
Secondary Master
Timeout
RO
Does not apply to PCI Express. Must be hardwired to 0b.
26
Master Timeout
Status
RO
Does not apply to PCI Express. Must be hardwired to 0b.
27
Discard Timer
SERR# enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
31:28
Reserved
RO
Reset to 0h.
7.2.29
POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Enhanced
Capabilities ID
RO
Read as 01h to indicate that these are power management enhanced capability
registers.
7.2.30
NEXT ITEM POINTER REGISTER – OFFSET 80h
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Next Item Pointer
RO
At upstream ports, the pointer points to the Vital Protocol Data (VPD)
capability register (9Ch).
At downstream ports, the pointer points to the Message capability register
(8Ch).
Reset to 9Ch (Upstream port).
Reset to 8Ch (Downstream port).
7.2.31
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h
BIT
FUNCTION
TYPE
DESCRIPTION
18:16
Power Management
Revision
RO
Read as 011b to indicate the device is compliant to Revision 1.2 of PCI
Power Management Interface Specifications.
19
PME# Clock
RO
Does not apply to PCI Express. Must be hardwired to 0b.
20
Reserved
RO
Reset to 0b.
21
Device Specific
Initialization
RO
Read as 0b to indicate Switch does not have device specific initialization
requirements. The default value may be changed by SMBus or auto-loading
from EEPROM.
24:22
AUX Current
RO
Reset as 111b to indicate the Switch needs 375 mA in D3 state. The default
value may be changed by SMBus or auto-loading from EEPROM.
25
D1 Power State
Support
RO
Read as 1b to indicate Switch supports the D1 power management state. The
default value may be changed by SMBus or auto-loading from EEPROM.
26
D2 Power State
Support
RO
Read as 1b to indicate Switch supports the D2 power management state. The
default value may be changed by SMBus or auto-loading from EEPROM.
31:27
PME# Support
RO
Read as 11111b to indicate Switch supports the forwarding of PME# message
in all power states. The default value may be changed by SMBus or auto-
loading from EEPROM.
7.2.32
POWER MANAGEMENT DATA REGISTER – OFFSET 84h
BIT
FUNCTION
TYPE
DESCRIPTION
1:0
Power State
RW
Indicates the current power state of the Switch. Writing a value of D0 when
the previous state was D3 cause a hot reset without asserting DWNRST_L.
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相關代理商/技術參數(shù)
參數(shù)描述
PI7C9X20404SLCFDEX 功能描述:外圍驅動器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20505GPBNDE 功能描述:外圍驅動器與原件 - PCI 5port 5lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20508GPANDE 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube
PI7C9X20508GPBEVB 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD - Boxed Product (Development Kits)
PI7C9X20508GPBNDE 功能描述:外圍驅動器與原件 - PCI 5port 8lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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