TM Family Datasheet Page 61 of 77 July 2009 – Rev" />
參數(shù)資料
型號(hào): PI7C9X20404SLCFDE
廠商: Pericom
文件頁(yè)數(shù): 58/77頁(yè)
文件大?。?/td> 0K
描述: IC PCIE PACKET SWITCH 128LQFP
標(biāo)準(zhǔn)包裝: 90
系列: SlimLine™
應(yīng)用: 封裝開關(guān),4 端口/4 線道
接口: PCI Express
封裝/外殼: 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 托盤
安裝類型: 表面貼裝
PI7C9X20404SL
4Port-4Lane PCI Express Switch
SlimLine
TM Family
Datasheet
Page 61 of 77
July 2009 – Revision 1.2
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
7
Bad DLLP Status
RW1CS
When set, the event of Bad DLLP has been received is detected.
Reset to 0b.
8
REPLAY_NUM
Rollover status
RW1CS
When set, the REPLAY_NUM Rollover event is detected.
Reset to 0b.
11:9
Reserved
RO
Reset to 000b.
12
Replay Timer
Timeout status
RW1CS
When set, the Replay Timer Timeout event is detected.
Reset to 0b.
13
Advisory Non-Fatal
Error status
RW1CS
When set, the Advisory Non-Fatal Error event is detected.
Reset to 0b.
31:14
Reserved
RO
Reset to 0b.
7.2.83
CORRECTABLE ERROR MASK REGISTER – OFFSET 114 h
BIT
FUNCTION
TYPE
DESCRIPTION
0
Receiver Error Mask
RWS
When set, the Receiver Error event is not logged in the Header Log register
and not issued as an Error Message to RC either.
Reset to 0b.
5:1
Reserved
RO
Reset to 00000b.
6
Bad TLP Mask
RWS
When set, the event of Bad TLP has been received is not logged in the Header
Log register and not issued as an Error Message to RC either.
Reset to 0b.
7
Bad DLLP Mask
RWS
When set, the event of Bad DLLP has been received is not logged in the
Header Log register and not issued as an Error Message to RC either.
Reset to 0b.
8
REPLAY_NUM
Rollover Mask
RWS
When set, the REPLAY_NUM Rollover event is not logged in the Header
Log register and not issued as an Error Message to RC either.
Reset to 0b.
11:9
Reserved
RO
Reset to 000b.
12
Replay Timer
Timeout Mask
RWS
When set, the Replay Timer Timeout event is not logged in the Header Log
register and not issued as an Error Message to RC either.
Reset to 0b.
13
Advisory Non-Fatal
Error Mask
RWS
When set, the Advisory Non-Fatal Error event is not logged in the Header
Long register and not issued as an Error Message to RC either.
Reset to 1b.
31:14
Reserved
RO
Reset to 0.
7.2.84
ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET
118h
BIT
FUNCTION
TYPE
DESCRIPTION
4:0
First Error Pointer
ROS
It indicates the bit position of the first error reported in the Uncorrectable
Error Status register.
Reset to 00000b.
5
ECRC Generation
Capable
RO
When set, it indicates the Switch has the capability to generate ECRC.
Reset to 1b.
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