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| 型號(hào)： | PM7383-PI |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | FRAME ENGINE AND DATA LINK MANAGER 32A256 |
| 中文描述： | 框架引擎和數(shù)據(jù)鏈路管理32A256 |
| 文件頁(yè)數(shù)： | 55/231頁(yè) |
| 文件大小： | 1947K |
| 代理商： | PM7383-PI |
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RELEASED
DATASHEET
PM7383 FREEDM-32A256
ISSUE 1
PMC-2010336
FRAME ENGINE AND DATA LINK MANAGER 32A256
PROPRIETARY AND CONFIDENTIAL
47
Links containing a T1/J1 or an E1 stream may be channelised. Data at each
time-slot may be independently assigned to a different channel. The RCAS256
performs a table lookup to associate the link and time-slot identity with a channel.
T1/J1 and E1 framing bits/bytes are identified by observing the gap in the link
clock which is squelched during the framing bits/bytes. For unchannelised links,
clock rates are limited to 51.84 MHz for links #0 to #2 and limited to 10 MHz for
the remaining links. All data on each link belongs to one channel. For the case
of a mixture of channelised, unchannelised and H-MVIP links, the total
instantaneous link rate over all the links is limited to 64 MHz. The RCAS256
performs a table lookup using only the link number to determine the associated
channel, as time-slots are non-existent in unchannelised links.
The RCAS256 provides diagnostic loopback that is selectable on a per channel
basis. The RCAS256 does not support diagnostic loopback for links configured
as H-MVIP. When a channel is in diagnostic loopback, stream data on the
received links originally destined for that channel is ignored. Transmit data of
that channel is substituted in its place.
8.3.1 Line Interface Translator (LIT)
The LIT block translates the information on the 32 physical links into a suitable
format for interpretation by the Line Interface block. The LIT block performs three
functions: data translation, clock translation and frame pulse generation.
When link 4m (0 m 7) is configured for operation in 8.192 Mbps H-MVIP mode,
the LIT block translates the 128 time-slots on link 4m to the Line Interface block
across links 4m, 4m+1, 4m+2 and 4m+3. The LIT block provides time-slots 0
through 31, 32 through 63, 64 through 95 and 96 through 127 to the Line
Interface block on links 4m, 4m+1, 4m+2 and 4m+3 respectively. When link 4m
is configured for operation in 8.192 Mbps H-MVIP mode, data cannot be received
on inputs RD[4m+3:4m+1]. However, links 4m+1, 4m+2 and 4m+3 must be
programmed in the RCAS256 Link Configuration register for 8.192 Mbps H-MVIP
operation. When links are configured for operation in 2.048 Mbps H-MVIP mode,
channelised T1/J1/E1 mode or unchannelised mode, the LIT block does not
perform any translation on the link data.
When a link is configured for operation in H-MVIP mode, the LIT block divides the
appropriate clock (RMVCK[n] for 2.048 Mbps H-MVIP and RMV8DC for 8.192
Mbps H-MVIP) by two and provides this divided down clock to the Line Interface
block. When a link is configured for operation in channelised T1/J1/E1 or
unchannelised mode, the LIT block does not perform any translation on the link
clock.
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PDF描述 |
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| PM7384 | Frame Engine and Data Link Manager |
| PM7384-BI | FRAME ENGINE AND DATA LINK MANAGER 84P672 |
| PM7385 | Frame Engine and Data Link Manager |
| PM7385-BI | 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER WITH ANY-PHY PACKET INTERFACE |
| PM7388 | Frame Engine and Datalink Manager |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PM7384 | 制造商:PMC 制造商全稱:PMC 功能描述:Frame Engine and Data Link Manager |
| PM7384-BI | 制造商:PMC 制造商全稱:PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER 84P672 |
| PM7385 | 制造商:PMC 制造商全稱:PMC 功能描述:Frame Engine and Data Link Manager |
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