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參數(shù)資料
| 型號： | PM7383-PI |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | FRAME ENGINE AND DATA LINK MANAGER 32A256 |
| 中文描述： | 框架引擎和數(shù)據(jù)鏈路管理32A256 |
| 文件頁數(shù)： | 67/231頁 |
| 文件大小： | 1947K |
| 代理商： | PM7383-PI |
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RELEASED
DATASHEET
PM7383 FREEDM-32A256
ISSUE 1
PMC-2010336
FRAME ENGINE AND DATA LINK MANAGER 32A256
PROPRIETARY AND CONFIDENTIAL
59
The partial packet buffer processor is divided into three sections: reader, writer
and roamer. The roamer is a time-sliced state machine which tracks each
channel’s FIFO buffer free space and signals the writer to service a particular
channel. The writer requests data from the TAPI256 block and transfers packet
data from the TAPI256 to the associated channel FIFO. The reader is a time-
sliced state machine which transfers the HDLC information from a channel FIFO
to the HDLC processor in response to a request from the HDLC processor. If a
buffer under-run occurs for a channel, the reader informs the HDLC processor
and purges the rest of the packet. If a buffer overflow occurs for a channel, the
THDL256 disables the channel as if it were unprovisioned and does not transmit
any further data until that channel is reprovisioned. In both cases, an interrupt is
generated and the cause of the interrupt may be read via the interrupt status
register using the microprocessor interface.
The writer and reader determine empty and full FIFO conditions using flags.
Each block in the partial packet buffer has an associated flag. The writer sets the
flag after the block is written and the reader clears the flag after the block is read.
The flags are initialized (cleared) when the block pointers are written using
indirect block writes. The reader declares a channel FIFO under-run whenever it
tries to read data from a block without a set flag.
The FIFO algorithm of the partial packet buffer processor is based on per-
channel software programmable transfer size and free space trigger level.
Instead of tracking the number of full blocks in a channel FIFO, the processor
tracks the number of empty blocks, called free space, as well as the number of
end of packets stored in the FIFO. Recording the number of empty blocks
instead of the number of full blocks reduces the amount of information the
roamer must store in its state RAM.
The partial packet roamer records the FIFO free space and end-of-packet count
for all channel FIFOs. When the reader signals that a block has been read, the
roamer increments the FIFO free space and sets a per-channel request flag if the
free space is greater than the limit set by XFER[3:0]. The roamer pushes this
status information to the TAPI256 to indicate that it can accept at least XFER[3:0]
blocks of data. The roamer also decrements the end-of-packet count when the
reader signals that it has passed an end of a packet to the HDLC processor. If
the HDLC processor is transmitting a packet and the FIFO free space is greater
than the free space trigger level and there are no complete packets within the
FIFO (end-of-packet count equal to zero), a per-channel starving flag is set. The
roamer searches the starving flags in a round-robin fashion to decide which
channel FIFOs are at risk of underflowing and pushes this status information to
the TAPI256. The roamer listens to control information from the TAPI256 to
decide which channel FIFO requests data from the TAPI256 block. The roamer
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相關(guān)代理商/技術(shù)參數(shù) |
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| PM7384-BI | 制造商:PMC 制造商全稱:PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER 84P672 |
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