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| 型號(hào)： | PM7383-PI |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | FRAME ENGINE AND DATA LINK MANAGER 32A256 |
| 中文描述： | 框架引擎和數(shù)據(jù)鏈路管理32A256 |
| 文件頁數(shù)： | 61/231頁 |
| 文件大?。?/td> | 1947K |
| 代理商： | PM7383-PI |
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RELEASED
DATASHEET
PM7383 FREEDM-32A256
ISSUE 1
PMC-2010336
FRAME ENGINE AND DATA LINK MANAGER 32A256
8.5.1 FIFO Storage and Control
PROPRIETARY AND CONFIDENTIAL
53
The FIFO block temporarily stores channel data during transfer across the Rx
APPI. RAPI256 burst data transfers are transaction based – a write burst data
transfer must be complete before any data will be read, and all data must be
completely read from the FIFO before any further data will be written into the
FIFO. To support full Rx APPI bus rate, a double buffer scheme is used. While
data is being read from one FIFO onto the Rx APPI, data can be written into the
other FIFO. Because the bandwidth on the writer side of the FIFOs is higher
than that on the reader side, the RAPI256 can maintain continuous full bandwidth
transfer over the Rx APPI.
A maximum of 256 bytes can be stored in one of the two FIFOs for any given
burst transfer. A separate storage element samples the 10 bit channel ID to
associate the data in that FIFO with a specific HDLC channel. This channel ID is
prepended in-band as the first word of every burst data transfer across the Rx
APPI. (The maximum length of a burst data transfer on the Rx APPI is therefore
129 words, including prepend.) The 3 most significant bits of the prepended
word of every burst data tansfer across the Rx APPI identify the FREEDM-
32A256 device associated with the transfer and reflect the value of the base
address programmed in the RAPI256 Control register.
The writer controller provides a means for writing data into the FIFOs. The writer
controller indicates that it can accept data when there is at least one completely
empty FIFO. In response, a complete burst transfer of data, up to a maximum of
256 bytes, is written into that empty FIFO. (The transfer is sourced by the
upstream RHDL256 block which selects from those channels with data available
using its round-robin algorithm.) The writer controller then informs the reader
controller that data is available in that FIFO. The writer controller now switches
to the other FIFO and repeats the process. When both FIFOs are full, the writer
throttles the upstream RHDL256 block to prevent of any further data writes into
the FIFOs.
The reader controller provides a means of reading data out of the FIFOs onto the
Rx APPI. When selected to do so, and the writer controller has indicated that at
least one FIFO is full, the reader controller will read the data out of the FIFOs in
the order in which they were filled. To prevent from overloading the Rx APPI with
several small bursts of data, the RAPI256 automatically deselects after every
burst transfer. This provides time for the upper layer device to detect an end of
packet indication and possibly reselect a different FREEDM-32A256 device
without having to store the extra word or two which may have been output onto
the Rx APPI during the time it took for deselection.
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相關(guān)代理商/技術(shù)參數(shù) |
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