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參數(shù)資料
| 型號： | PM7383-PI |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | FRAME ENGINE AND DATA LINK MANAGER 32A256 |
| 中文描述： | 框架引擎和數(shù)據(jù)鏈路管理32A256 |
| 文件頁數(shù)： | 68/231頁 |
| 文件大?。?/td> | 1947K |
| 代理商： | PM7383-PI |
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RELEASED
DATASHEET
PM7383 FREEDM-32A256
ISSUE 1
PMC-2010336
FRAME ENGINE AND DATA LINK MANAGER 32A256
PROPRIETARY AND CONFIDENTIAL
60
informs the partial packet writer of the channel FIFO to process and the FIFO
free space. The writer sends a request for data to the TAPI256 block and writes
the response data to the channel FIFO setting block full flags. The writer reports
back to the roamer the number of blocks and end-of-packets transferred. The
maximum amount of data transferred during one request is limited by a software
programmable limit.
The roamer round-robins between all channel FIFOs and pushes the status to
the TAPI256 block. The status consists of two pieces of information: (1) is there
space in the channel FIFO for at least one XFER[3:0] of data, and (2) is this
channel FIFO at risk of underflowing. Where a channel FIFO is at risk of
underflowing, the THDL256 pushes a starving status for that channel FIFO to the
TAPI256 at the earliest possible opportunity.
The configuration of the HDLC processor is accessed using indirect channel read
and write operations as well as indirect block read and write operations. When
an indirect operation is performed, the information is accessed from RAM during
a null clock cycle identified by the TCAS256 block. Writing new provisioning data
to a channel resets the entire state vector.
8.8 Transmit Channel Assigner
The Transmit Channel Assigner block (TCAS256) processes up to 256 channels.
Data for all channels is sourced from a single byte-serial stream from the
Transmit HDLC Controller / Partial Packet Buffer block (THDL256). The
TCAS256 demultiplexes the data and assigns each byte to any one of 32 links.
Each link may be configured to support 2.048 or 8.192 H-MVIP traffic, to support
T1/J1/E1 channelised traffic or to support unchannelised traffic. When
configured to support H-MVIP traffic, each group of 8 links share a clock and
frame pulse, otherwise each link is independent and has its own associated
clock. For each high-speed link (TD[2:0]), the TCAS provides a six byte FIFO.
For the remaining links (TD[31:3]), the TCAS provides a single byte holding
register. The TCAS256 also performs parallel to serial conversion to form a bit-
serial stream. In the event where multiple links are in need of data, TCAS256
requests data from upstream blocks on a fixed priority basis with link TD[0]
having the highest priority and link TD[31] the lowest.
From the point of view of the TCAS256, links configured for H-MVIP traffic
behave identically to links configured for T1/J1/E1 channelised or unchannelised
traffic in the back end, only differing on the link side as described herein. First,
the number of time-slots in each frame is programmable to be 32 or 128 and has
an associated data clock frequency that is double the data rate. This provides
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