參數(shù)資料
型號: PSB7110
廠商: SIEMENS AG
英文描述: Enhanced ISDN Data Access Controller ISAR
中文描述: 增強綜合業(yè)務(wù)數(shù)字網(wǎng)的數(shù)據(jù)接入控制器專家組
文件頁數(shù): 19/164頁
文件大小: 1173K
代理商: PSB7110
_________________________________________________PSB 7110
Siemens Aktiengesellschaft
Page 19
1.6
Clock Generation
The chip internal clocks are derived from a crystal connected across XTAL1 and XTAL2 or from an
external clock input via pin XTAL1.
In the ISAR V1.0 no PLL is available. Therefore, for the internal DSP clock an external crystal of
30.72 MHz is required and the clock mode pins have to be connected as shown in the figure below,
i.e. CM1 = 1 , CM0 = 0 .
SRAM
32K X 16
DD
DU
DCL
FSC
Transceiver
Interface Logic (PnP, ISA)
or
Microcontroller
Power
Supply
Clock
Generation
PSB 7110 V1.0
(7110_28)
Figure 8 Clock generation
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