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參數(shù)資料
| 型號： | PSB7110 |
| 廠商： | SIEMENS AG |
| 英文描述： | Enhanced ISDN Data Access Controller ISAR |
| 中文描述： | 增強綜合業(yè)務數(shù)字網(wǎng)的數(shù)據(jù)接入控制器專家組 |
| 文件頁數(shù)： | 28/164頁 |
| 文件大?。?/td> | 1173K |
| 代理商： | PSB7110 |
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_________________________________________________PSB 7110
Siemens Aktiengesellschaft
Page 28
2.3
SART Configuration
The SART (Synchronous Asynchronous Receiver Transmitter) can be configured for ASYNC character formatting,
HDLC bit level formatting and binary mode. i.e. no bit level formatting.
2.3.1
ASYNC Mode
ASYNC denotes an asynchronous formatting of data according to ITU-T specification V.14.
In ASYNC mode, the SART adds start, parity and stop bits to each data byte. The following options are
programmable:
Character Length:
No. of stop bits:
Parity:
Overspeed range:
5,6,7,8 Bit
1,2
No, odd, even, stick parity
12.5 or 25 % (stop bit deletion: 1 of 8, 1 of 4)
The ASYNC formatter performs overspeed handling according to V.14. Therefore a stop bit may be deleted
according to the overspeed range.
The ASYNC formatter is able to generate a break signal and to detect a break signal of a minimum length of 2M+3
bits of start bit polarity.
A special option is included to generate V.42 detection timing.
In receive direction the character format is controlled and errors are reported via the mailbox. These errors may be
framing error (missing stop bit) and parity error.
In receive direction, the character data is extracted, format check is performed and the character data is written to the
buffer. If a framing or parity error has been detected or if a break signal has been received, a message can be read
from the mailbox by the host even though the programmed message length may not yet be complete, i.e. the new
message may be shorter than the programmed length.
For configuration setup the host has to distinguish two ASYNC modes which do not differ in functionality, but depend
on the selected pump mode.
2.3.2
HDLC Mode
In HDLC mode, the SART generates/handles the HDLC frame formatting. This includes opening and closing flag,
CRC generation/detection and zero-bit insertion.
Programmable features are:
CRC:
Inter frame timefill:
Bit stream coding:
Data underrun operation:
16 Bit
'1' or flags
regular, inverse
Abort generation / frame end (CRC+flag) generation
In transmit direction a frame is started after SART data is available in the transmit FIFO buffer. The frame is
continued until a frame end mark has been set in a mailbox command. In this case, the HDLC frame is closed by the
CRC value and a closing flag. In case a buffer underrun occurs, the current HDLC frame is closed either by an abort
sequence or by CRC and closing flag (programmable).
In receive direction, HDLC frames exceeding the programmed message length are transferred to/from the buffer in
data blocks of the configured message length. A message of reduced length may be transferred if a frame start,
frame end or error condition is detected. In this case the control word contains the result of the CRC check,
verification of integer number of bytes and check of frame end condition.
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