參數(shù)資料
型號(hào)： PSB7110
廠商： SIEMENS AG
英文描述： Enhanced ISDN Data Access Controller ISAR
中文描述： 增強(qiáng)綜合業(yè)務(wù)數(shù)字網(wǎng)的數(shù)據(jù)接入控制器專家組
文件頁數(shù)： 23/164頁
文件大?。?/td> 1173K
代理商： PSB7110
_________________________________________________PSB 7110
Siemens Aktiengesellschaft
Page 23
2.1.2.3
Communications Interface
The ISAR provides a communication interface in terms of a 61 byte mailbox per direction, a 16 bit control word and
an 8 bit interrupt register.
Besides that, there is an interrupt mask/status bit (bit 2 of register 75h) and two interrupt acknowledge bits (LSB of
address location 50h and 58h respectively).
The address map is shown in figure 11 . All other address locations are reserved for further use.
50h
58h
60h
61h
ISAR Interrupt Status (IIS)
Host Write
Host Read
Host Interrupt Status (HIS)
ISAR Control Register Low
Host Control Register Low
Host Control Register High
ISAR Control Register High
Address
AD0...AD7
HIA
IIA
48h
4Ah
4Ch
Mailbox read address
Mailbox read address
Mailbox write address
Mailbox write address
Mailbox I/O data
Mailbox I/O data
MSK
STA
Bit
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
75h
(7110_22)
Figure 11 Host Interface Registers
Interrupt Mask / Status Bit (75h Write/Read)
All interrupt sources can be masked by setting the MSK-bit to "0", so that no interrupt is indicated to the host. In such
a case the status STA-bit can be polled to check whether an interrupt occurred. After reset the interrupt is masked,
however, the mask bit affects only the generation of the interrupt, but not the interrupt status bit from being set.
When setting the MSK-bit, all other bits in reg. 75h are not don't care, but must be set to "0". After reset all interrupts
are masked (MSK = 0).
Mailbox
The mailbox is implemented as physically two separate 61-byte memory blocks. As for the ISAR V1.1 (ROM version)
the mailbox size will be increased, the host can request information about the mailbox size from the ISAR and so
allow for software compatibility with future versions.
The mailbox is seen from the host as an I/O device. Thus, to read/write a byte from/to the Mailbox, the host accesses
a single location (Mailbox I/O data), which is the same address but physically separate location for read and for write
direction.
The address is given by an address register directly programmable by the host (Mailbox read/write address). This
address is autoincremented every time an access by the host to Mailbox I/O data is performed. Thus, for sequential,
fast access, the host only needs to set the start address for the first message byte and all subsequent data bytes can
be read/written without reprogramming its address.
For random access to the Mailbox the Host has to reprogram the address register(s).
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