
_________________________________________________PSB 7110
Siemens Aktiengesellschaft
Page 22
2.1.1
Clock Generation
The clock generator provides the internal master clock for the fax/modem engine derived from an input clock or
crystal at pins XTAL(1:2).
Other blocks derive their clock signal directly from the IOM-2 interface.
2.1.2
Interfaces
The PSB 7110 provides two physical interfaces: The IOM-2 interface and the host interface.
2.1.2.1
IOM-2 Interface
The IOM-2 interface is a 4-wire interface with two open drain data lines (DU and DD), a data clock input (DCL) and a
frame sync signal input (FSC), of which the rising edge indicates the start of an IOM-2 frame (8 kHz). For IOM-2
applications the data clock is typically set to twice the data rate.
The PSB 7110 supports the IOM-2 terminal and line-card mode.
IOM-2 Driver
The output driver of the DD and DU pins is open drain. The output drivers are active for the selected time-slot bits
and remain tri-state during the rest of the frame.
The control lines FSC and DCL are input.
IOM-2 Timeslots used by the PSB 7110
The ISAR separates IOM-2 terminal mode from IOM-2 line card mode. In terminal mode, the three channel IOM-2
structure is used. In line-card mode, eight IOM channels can be programmed with flexible time-slot assignment of the
B-channel data.
The PSB 7110 is able to make extensive use of the IOM-2 channels as it is able to access all user data timeslots by
programming the timeslot number and bit shift.
For detailed information refer to the "IOM-2 Interface Reference Guide".
2.1.2.2
Host Inter face
The PSB 7110 provides a host interface which consists of an 8-bit multiplexed address/data bus. Data transfer is
controlled by a chip select signal and read or write control signals.
An interrupt line may be activated to indicate to the host that service is required.
Symbol
In (I)
Out (O)
Function
AD(0:7)
I/O
Address/Data Bus.
Transfers addresses and data between the host and the ISAR PSB 7110.
Read.
This signal indicates a read operation.
Write.
This signal indicates a write operation.
Chip Select.
Address Latch Enable.
A "high" on this line indicates an address on AD(0:7).
Interrupt Request
Interrupt output line for all mailbox interrupt status.
RD#
I
WR#
I
CS#
ALE
I
I
INT#
O (OD)
Data transfer between the host and the PSB 7110 is performed by use of a 61 byte mailbox per direction.