參數(shù)資料
型號(hào)： PSB7110
廠商： SIEMENS AG
英文描述： Enhanced ISDN Data Access Controller ISAR
中文描述： 增強(qiáng)綜合業(yè)務(wù)數(shù)字網(wǎng)的數(shù)據(jù)接入控制器專家組
文件頁(yè)數(shù)： 25/164頁(yè)
文件大?。?/td> 1173K
代理商： PSB7110
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_________________________________________________PSB 7110
Siemens Aktiengesellschaft
Page 25
Buffer 1 and 2 use a SART (Synchronous Asynchronous Receiver Transmitter) which supports ASYNC, HDLC and
binary mode. In ASYNC mode, the characters are formatted according to the
ITU-T V.14 standard by start, parity and stop bits. In HDLC mode, the HDLC bit level functions (Flag, CRC, Zero-bit
handling) are performed.
Binary mode describes a synchronous, transparent mode without formatting.
Each buffer is controlled by a set of operations which relate to:
Configuration data
Status data
User data transfer
Transmit direction
For consistent data transfer from the host to the ISAR, the following protocol should be used. Additionally the internal
procedure at the ISAR is shown as well.
HOST
ISAR
*
read HIA-bit,
wait until HIA=0 (indicates that the host write
mailbox registers are available)
reset mailbox write address to 0 (only if data is
written to the mailbox)
write to Host control word and
to mailbox
write command to HIS-register,
that causes setting of HIA-bit
polling for HIA=0 (see first entry)
*
polling HIS-register periodically
*
*
*
*
*
read HIS-register, Host control word and mailbox
write HIA=0 (indicates that the ISAR has read all
mailbox registers, i.e. the host may start a new
data transfer)
HIS
HIA
Host Interrupt Status
Host Interrupt Acknowledge
In transmit direction, these operations are performed by the host by writing the corresponding interrupt status byte
into the Host Interrupt Status register (HIS). Additional information may be written to the Host control word and to the
mailbox if required.
The general format of the Host control word is for the high byte to contain control, configuration or status information
(additionally to the host interrupt status byte) while the low byte is used to indicate the number of valid bytes in the
mailbox.
Once the Interrupt Status byte as well as control word and mailbox have been written, the Host Interrupt
Acknowledge bit (HIA) will be set automatically (when writing the Host Interrupt Status) to indicate the new contents
to the ISAR.
After ISAR has completed the evaluation of the mailbox contents, the mailbox is released by the ISAR when resetting
the Host Interrupt Acknowledge bit (HIA), so the host may enter new mailbox data.
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PSB71F04 制造商:POWERSEM 制造商全稱:POWERSEM 功能描述:Single Phase Rectifier Bridge with fast Recovery Epitaxial Diode (FRED)
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