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參數(shù)資料
| 型號： | PT7D6555 |
| 英文描述： | -40V Single P-Channel HEXFET Power MOSFET in a TSOP-6 (Micro 6) package |
| 中文描述： | 擴展的PCM接口控制器？ |
| 文件頁數(shù)： | 15/56頁 |
| 文件大?。?/td> | 489K |
| 代理商： | PT7D6555 |
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Preliminary Data Sheet
PT7D6555
Extended PCM Interface Controller
15
PT0105(08/02)
Ver:0
Figure 10. IOM - 2 Frame Structure with 2.048 Mbit/s Data Rate
Memory Structure and Switching
The memory block of the PT7D6555 performs the switching
functionality.
It consists of four sub blocks:
·
Upstream data memory
·
Downstream data memory
·
Upstream control memory
·
Downstream control memory.
The PCM-interface reads periodically from the upstream (writes
periodically to the downstream) data memory (cyclical ac-
cess), see figure 11.
The CFI reads periodically the control memory and uses the
extracted values as pointers to write to the upstream (read from
the downstream) data memory (random access). In the case of
C/I- or signaling channel applications the corresponding data
is stored in the control memory. In order to select the applica-
tion of choice, the control memory provides a code portion.
The control memory is accessible via the
μ
P-interface. In order
to establish a connection between CFI time slot A and PCM-
interface time slot B, the B-pointer has to be loaded into the
control memory location A.
Figure 11. Memory Structure
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