- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368349 > PT7D6555 -40V Single P-Channel HEXFET Power MOSFET in a TSOP-6 (Micro 6) package PDF資料下載
參數(shù)資料
| 型號： | PT7D6555 |
| 英文描述： | -40V Single P-Channel HEXFET Power MOSFET in a TSOP-6 (Micro 6) package |
| 中文描述： | 擴展的PCM接口控制器？ |
| 文件頁數(shù)： | 45/56頁 |
| 文件大?。?/td> | 489K |
| 代理商： | PT7D6555 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁當前第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Preliminary Data Sheet
PT7D6555
Extended PCM Interface Controller
45
PT0105(08/02)
Ver:0
Operation Mode Register (OMDR) Address: 1EH/3EH(X/FH) Read/Write
Value after reset: 00000000B
7 0
OMS1
OMS0
PSB
PTL
COS
MFPS
CSB
RBS
PSB
PCM Standby.
0
…
the PCM interface output pins TxD0..3 are set to high impedance and those TSC pins that are actually used as
tristate control signals are set to logical 1 (inactive).
1
…
the PCM output pins transmit the contents of the upstream data memory or may be set to high impedance via the
data memory tristate field.
PCM Test Loop.
0
…
the PCM test loop is disabled.
1
…
the PCM test loop is enabled, i.e. the physical transmit pins TxD# are internally connected to the corresponding
physical receive pins RxD#, such that data transmitted over TxD# are internally looped back to RxD# and data
externally received over RxD# are ignored. The TxD# pins still output the contents of the upstream data memory
according to the setting of the tristate field (only modes 0 and 1; mode 1 with AIS bit set).
CFI Output driver Selection.
0
…
the CFI output drivers are tristate drivers.
1
…
the CFI output drivers are open drain drivers.
Monitor/Feature control channel Protocol Selection.
0
…
handshake facility disabled (SLD and IOM-1 applications)
1
…
handshake facility enabled (IOM-2 applications)
CFI Standby.
0
…
the CFI interface output pins DD0..3, DU0..3, DCL and FSC are set to high impedance.
1
…
the CFI output pins are active.
Register Bank Selection. Used in demultiplexed data/address modes only.
0
…
to access the registers used during device operation
1
…
to access the registers used during device initialization.
OMS1..01
Operational Mode Selection;
these bits determine the operation mode of the PT7D6555 according to the
following table:
PTL
COS
MFPS
CSB
RBS
OMS1, 0
00
Function
The
CM reset mode
is used to reset all locations of the control memory code and data
fields with a single command within only 256 RCL cycles. A typical application is
resetting the CM with the command MACR = 70 H which writes the contents of MADR
(XXH) to all data field locations and the code 0000 (unassigned channel) to all code field
locations. A CM reset should be made after each hardware reset. In the CM-reset mode the
PT7A6555 does not operate normally i.e. the CFI- and PCM-interfaces are not operational.
The
CM initialization mode
allows fast programming of the control memory since each
memory access takes a maximum of only 2.5 RCL cycles compared to the 9.5 RCL cycles
in the normal mode. Accesses are performed on individual addresses specified by MAAR.
The initialization of control/signaling channels in IOM or SLD applications can for
example be carried out in this mode. In the CM initialization mode the PT7A6555 does
also not work normally.
In the
normal operation mode
the CFI and PCM interfaces are operational. Memory
accesses performed on single addresses (specified by MAAR) take 9.5 RCL cycles. An
initialization of the complete data memory tristate field takes 1035 RCL cycles.
In
test mode
the PT7A6555 sustains normal operation. However memory accesses are no
longer performed on a specific address defined by MAAR, but on all locations of the
selected memory, the contents of MAAR (including the U/D bit!) being ignored. A test
mode access takes 2057 RCL cycles.
10
11
01
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PT7M7803RT | μP Supervisor Circuits? |
| PT7V2727 | 3.3v/5.0v operating voltage |
| PT7V2727W | 3.3v/5.0v operating voltage |
| PT7V3727W | 3.3v/5.0v operating voltage |
| PT7V4027W | 3.3V operating voltage |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PT7FFSDGY | 制造商:Hubbell Wiring Device-Kellems 功能描述:FLUSH FRPT, 1 SERV, FURN FEED, GY |
| PT7FFSDI | 制造商:Hubbell Wiring Device-Kellems 功能描述:FLUSH FRPT, 1 SERV, FURN FEED, IV |
| PT7FSD | 制造商:Hubbell Wiring Device-Kellems 功能描述:THRU-FLOOR FITTING, 3 FLUSH FRPT |
| PT7FSDBLA | 制造商:Hubbell Wiring Device-Kellems 功能描述:FLUSH FRPT, W/20A DUP/TELE/DATA,BK |
| PT7FSDBRA | 制造商:Hubbell Wiring Device-Kellems 功能描述:FLUSH FRPT, W/20A DUP/TELE/DATA,BR |
發(fā)布緊急采購，3分鐘左右您將得到回復。