參數(shù)資料
型號: PT7D6555
英文描述: -40V Single P-Channel HEXFET Power MOSFET in a TSOP-6 (Micro 6) package
中文描述: 擴展的PCM接口控制器?
文件頁數(shù): 51/56頁
文件大?。?/td> 489K
代理商: PT7D6555
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Preliminary Data Sheet
PT7D6555
Extended PCM Interface Controller
51
PT0105(08/02)
Ver:0
PCM and Configurable Interface Timing
Sym
t
CP
Description
Test Condition
Min
240
Typ
Max
Unit
ns
Clock period
t
CPL
Clock period low
80
ns
t
CPH
Clock period high
Clock frequency <
4096KHz
100
ns
t
CP
Clock period
120
ns
t
CPL
Clock period low
50
ns
t
CPH
Clock period high
Clock frequency >
4096KHz
50
ns
t
FS
Frame set-up time to clock
25
ns
t
FH
Frame hold time from clock
50
ns
t
DCD
Data clock delay
2)
125
ns
t
S
Serial data input set-up time
(falling clock edge)
Serial data input set-up time
(rising clock edge)
Serial data hold time
7
ns
t
S
15
ns
t
H
PCM-input data
requency>4096 kbit/s
35
ns
t
S
Serial data input set-up time
15
ns
t
H
Serial data hold time
PCM-input data
requency<4096 kbit/s
55
ns
t
S
Serial data input set-up time
20
ns
t
H
Serial data hold time
CFI-input data
requency<4096 kbit/s
50
ns
t
S
Serial data input set-up time
0
ns
t
H
Serial data hold time
CFI-input data
requency<4096 kbit/s
75
ns
t
D
PCM-serial data output delay
1)
55
ns
t
T
Tristate control delay
1)
60
ns
t
CDF
CFI-serial data output delay
Falling clock edge 2)
65
ns
t
CDR
CFI-serial data output delay
Rising clock edge 2)
90
ns
Note: 1) Parameter can be estimated to: 20 ns + 0.25 ns x [C
L
]
2) The max. difference between t
DCD
and t
CDF
/ t
CDR
is 60 ns / 35 ns
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