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參數(shù)資料
| 型號： | PT7D6555 |
| 英文描述： | -40V Single P-Channel HEXFET Power MOSFET in a TSOP-6 (Micro 6) package |
| 中文描述： | 擴展的PCM接口控制器？ |
| 文件頁數(shù)： | 17/56頁 |
| 文件大小： | 489K |
| 代理商： | PT7D6555 |
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Preliminary Data Sheet
PT7D6555
Extended PCM Interface Controller
17
PT0105(08/02)
Ver:0
Operational Description
The PT7D6555, designed as a flexible line-card controller, has
the following main applications:
-
Digital line cards, with the CFI typically configured as
IOM-2, IOM-1 (MUX) or SLD.
-
Analog line cards, with the CFI typically configured as
IOM-2 or SLD.
-
Key systems, where the PT7A6555
’
s ability to mix CFI
configurations is utilized.
To operate the PT7D6555 the user must be familiar with the
device
’
s microprocessor interface, interrupt structure and reset
logic.
Microprocessor Interface Operation
The PT7D6555 is programmed via an 8-bit parallel interface
that can be selected to be
(1) Motorola type, with control signals DS, R/W and CS.
(2) Intel non-multiplexed bus type, with control signals WR,
RD and CS.
(3) Intel multiplexed address/data bus type, with control
signals ALE, WR, RD, and CS.
The selection is performed via pin ALE as follows:
ALE tied to Vcc
(1)
ALE tied to GND
(2)
Edge on ALE
(3)
The occurrence of an edge on ALE, either positive or negative,
at any time during the operation immediately selects interface
type (3). A return to one of the other interface types is only
possible by issuing hardware reset.
In order to simplify the use of 8- and 16-bit Intel type CPUs,
different register addresses are defined in multiplexed and
demultiplexed bus mode. In the multiplexed mode even ad-
dresses are used (AD0 always 0).
For a demultiplexed
μ
P interface mode the OMDR: RBS bit is
needed in addition to the address lines A3-A0. With OMDR:
RBS (register bank selection) one of two register banks is se-
lected.
RBS =
“
1
”
selects a set of registers used for device initial-
ization (e.g. CFI and PCM interface initialization).
RBS =
“
0
”
switches to a group of registers necessary dur-
ing operation (e.g. connection programming).
The OMDR register containing the RBS bit can be accessed
with either value of RBS.
Interrupts
An interrupt of the PT7D6555 is indicated by activating the
INT line. The detailed cause of the request can be determined
by reading the ISTA register. The INT output is level active. It
remains active until all interrupt sources have been serviced. If
a new status bit is set while an interrupt is being serviced, the
INT remains active. When using an edge-triggered interrupt
controller, it is thus recommended to rewrite the MASK-regis-
ter at the end of any interrupt service routine.
Every interrupt source can be selectively masked by setting
the respective bit of the MASK register. Such masked inter-
rupts will not be indicated in the ISTA register, nor will they
activate the INT line.
Clocking
To operate properly, the PT7D6555 always requires a PDC-
clock. To synchronize the PCM side, the PT7D6555 should
normally also be provided with a PFS strobe. In most applica-
tions, the DCL and FSC will be output signals of the PT7D6555,
derived from the PDC via prescalers.
If the required CFI data rate cannot be derived from the PDC,
DCL and FSC can also be programmed as input signals. This is
achieved by setting the PT7D6555 CMD1: CSS-bit. Frequency
and phase of DCL and FSC may then be chosen almost inde-
pendently of the frequency and phase of PDC and PFS. How-
ever, the CFI clock source must still be synchronous to the
PCM-interface clock source; i.e. the clock source for the CFI
interface and the clock source for the PCM-interface must be
derived from the same master clock.
Reset
A reset pulse of at least 4 PDC clock cycles has to be applied at
the RES pin. The reset pulse sets all registers to their reset
values described in section
Registers
.
The PT7D6555 is now in CM reset mode. As the hardware reset
does not affect the PT7D6555 memories CM and DM, a
“
soft-
ware reset
”
of the CM has to be performed. Subsequently the
PT7D6555 can be programmed to CM initialization, normal
operation or test mode. During reset the address latch enable
pin ALE is evaluated to determine the bus interface type.
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