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Preliminary Data Sheet
PT7D6555
Extended PCM Interface Controller
7
PT0105(08/02)
Ver:0
Pin No.
Name
Input (I)
Output (O)
Open
Drain (OD)
Function
30
CS
I
Chip Select
, active low. A low on this line selects the PT7D6555 for
read/write operations.
Address Latch Enable
ALE controls the on chip address latch in multiplexed bus mode. While ALE is
high , the latch is transparent. The falling edge latches the current address.
During the first read/write access following reset ALE is evaluated to select the
bus mode.
Interrupt Request
, active low.
This signal is activated when the PT7D6555 requests an interrupt. Due to the
open drain (OD) characteristic of INT multiple interrupt sources can be
connected together.
31
ALE
I
32
INT
OD
33
DCL
I/O
Data Clock
Input or output in IOM, slave clock in SLD configuration. In IOM configuration
single or double data rate, single data rate in SLD mode.
34
FSC
I/O
Frame Synchronization
Input or output in IOM configuration. Direction indication signal in SLD mode.
Data Upstream Input
, IOM or PCM configuration.
Serial Interface Port
, SLD configuration.
Depending on the bit OMDR: COS these lines have push pull or open drain
characteristic.
For unassigned channels or when bit OMDR: CSB is reset the pins are in the
state high impedance.
38
37
36
35
DU0/SIP4
DU1/SIP5
DU2/SIP6
DU3/SIP7
I/IO(OD)
40
41
42
43
DD0/SIP0
DD1/SIP1
DD2/SIP2
DD3/SIP3
O/IO(OD)
Data Downstream Output
, IOM or PCM configuration.
Serial Interface Port
, SLD configuration.
Depending on the bit OMDR: COS these lines have push pull or open drain
characteristic. For unassigned channels or when bit OMDR: CSB is reset the pins
are in the high impedance state.
44
RES
I
Reset
A high forces the PT7D6555 into reset state.