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參數(shù)資料
| 型號： | PT7D6555 |
| 英文描述： | -40V Single P-Channel HEXFET Power MOSFET in a TSOP-6 (Micro 6) package |
| 中文描述： | 擴展的PCM接口控制器？ |
| 文件頁數(shù)： | 20/56頁 |
| 文件大?。?/td> | 489K |
| 代理商： | PT7D6555 |
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Preliminary Data Sheet
PT7D6555
Extended PCM Interface Controller
20
PT0105(08/02)
Ver:0
(CMD2 register). The CFI offset function shifts both the frame
and the FSC output signal with respect to the PFS signal.
In the second case, the CFI data rate is derived from the DCL-
clock, which is now used as an input signal. The DCL clock
may also first be divided down by internal prescalers before it
serves as the CFI reference clock CRCL and before defining
the CFI data rate. The framing signal FSC is used to synchro-
nize the CFI frame structure.
Switching Function
The major tasks of the PT7D6555 part is to dynamically switch
PCM data between the serial PCM interface, the serial
configurable interface (CFI) and the parallel
μ
P interface. All
possible switching paths are shown in figure 12.
CFI - PCM Time Slot Assignment
Switching paths 1 and 2 of figure 12 can be realized for a total
number of 128 channels per path, i.e. 128 time slots in up-
stream and 128 time slots in downstream direction. To estab-
lish a connection, the
μ
P writes the addresses of the involved
CFI and PCM time slots to the control memory. The actual
transfer is then carried out frame by frame without further
μ
P
intervention.
The switching paths 5 and 6 can be realized by programming
time slot assignments in the control memory. The total number
for such loops is limited to the number of available time slots
Figure 12. Switching Paths inside the PT7D6555
Note:
The time slot selections in upstream direction are completely independent of the time slot selections in downstream
direction.
at the respective opposite interface, i.e. looping back a time
slot from CFI to CFI requires a spare upstream PCM time slot
and looping back a time slot from PCM to PCM requires a
spare downstream and upstream CFI time slot.
Time slot switching is always carried out on 8-bit time slots,
the actual position and number of transferred bits can however
be limited to 4-bit or 2-bit sub time slots within these 8-bit
time slots. On the CFI side, only one sub time slot per 8-bit
time slot can be switched, whereas on the PCM-interface up to
4 independent sub time slots can be switched.
Sub Time Slot Switching
Sub time slot positions at the PCM-interface can be selected at
random, i.e. each single PCM time slot may contain any mix-
ture of 2- and 4-bit sub time slots. A PCM time slot may also
contain more than one sub time slot. On the CFI however, two
restrictions must be observed:
·
Each CFI time slot may contain one and only one sub
time slot.
·
The sub-slot position for a given bandwidth within
the time slot is fixed on a per port basis.
μ
P Transfer
Switching paths 3 and 4 of figure 12 can be realized for all
available time slots. Path 3 can be implemented by defining
the corresponding CFI time slots as
“
μ
P channels
”
or as
“
pre-
processed channels
”
.
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