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參數(shù)資料
| 型號： | PT7D6555 |
| 英文描述： | -40V Single P-Channel HEXFET Power MOSFET in a TSOP-6 (Micro 6) package |
| 中文描述： | 擴(kuò)展的PCM接口控制器？ |
| 文件頁數(shù)： | 40/56頁 |
| 文件大?。?/td> | 489K |
| 代理商： | PT7D6555 |
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Preliminary Data Sheet
PT7D6555
Extended PCM Interface Controller
40
PT0105(08/02)
Ver:0
MF-Channel Subscriber Address Register (MFSAR) Address: 14H(0/AH) Write
Value after reset: XXXXXXXXB
7 0
MFTC1 MFTC0 SAD5
SAD4
SAD3
SAD2
SAD1
SAD0
The exchange of monitor data normally takes place with only one subscriber circuit at a time. This register serves to point the
MF handler to that particular CFI time slot.
MFTC1..0 MF Channel Transfer Control 1..0; these bits, in addition to CMDR: MFT1, 0 and OMDR: MFPS control the
MF channel transfer as indicated in table 6.
SAD5..0 Subscriber address 5
…
0; these bits define the addressed subscriber. The CFI time slot encoding is similar to the
one used for Control Memory accesses using the MAAR register (tables 3 and 4):
CFI time slot encoding of MFSAR derived from MAAR:
MAAR:
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
MFSAR:
MFTC1 MFTC0 SAD5
SAD4
SAD3
SAD2
SAD1
SAD0
MAAR: MA7 selects between upstream and downstream CM blocks. This information is not required since the transfer direc
tion is defined by CMDR (transmit or receive).
MAAR: MA0 selects between even and odd time slots. This information is also not required since MF channels are always
located on even time slots.
Monitor/Feature Control Channel FIFO (MFFIFO) Address: 16H(0/BH) Read/Write
Value after reset: empty
7 0
MFD7
MFD6
MFD5
MFD4
MFD3
MFD2
MFD1
MFD0
The 16-byte bi-directional MFFIFO provides intermediate storage for data bytes to be transmitted or received over the monitor
or feature control channel.
MFD7..0 MF Data bits 7..0; MFD7 (MSB) is the first bit to be sent over the serial CFI, MFD0 (LSB) the last.
Note:
The byte n + 1 of an n-byte transmit message in monitor channel is not defined.
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