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參數(shù)資料
| 型號(hào)： | PXB4350E |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | ICs for Communications |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 127/185頁(yè) |
| 文件大?。?/td> | 2552K |
| 代理商： | PXB4350E |
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3;%(
Data Sheet
4-127
04.2000
2SHUDWLRQ
data from a former RMW cycle is lost during write-only-access (bit 0 of register RMWC equal to
’1’). During read or modify the external RAM parity-check will be done. While RMW is active, the
registers RMWC and RMWADR are writeprotected.
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When the microprocessor should insert cells, e.g. PM or CC, follow this guideline :
1.
Write the cell data into the transmit cell payload registers TXR0..26 (see
VHFWLRQ
page 67 and
VHFWLRQ
page 68).
2.
If the cell is to be inserted in downstream direction set bit 0 of the transmission command
register TMCR (see
VHFWLRQ
page 69). Otherwise set bit 1 (for upstream direction).
If both bits are set to ’1’, the AOP reacts in the same way as if only bit 1 is set.
3.
After the insertion of the microprocessor cell into the datastream, the choosen bit in register
TMCR will be reset by the AOP.
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If a cell arrives at the AOP, the microprocessor must perform the following operations :
1.
The AOP signals the availability of arrived cells by setting bit 9 of the interrupt register ISR0
(see
VHFWLRQ
page 83).
2.
The microprocessor has to read the receive cell register RXRCEL for 27 times.
3.
Bit 6 of the UDF2 octed will indicate the source of the arrived cell (’0’ = downstream).
4.
After the 27th read access the AOP will reset bit 9 of ISR0.
The cell will be read in the same order as the transmit cell, i.e. address 80 to 9C.
6&$1XVDJH
Here is an example for the usage of the SCAN.
1.
Setup the connections in the external RAM using RMW.
2.
For general adjustement of the SCAN procedure, the microprocessor has to write the first
LCI to be processed into register SCCONF4 (see
VHFWLRQ
to be processed into register SCCONF5 (see
VHFWLRQ
for SCP and SCPTOL into register SCCONF2 (see
VHFWLRQ
page 48). Further some adjustments for DMA are needed when use of DMA is
intended. Set bit 3 of the DMA configuration register DCONF (see
VHFWLRQ
to the respective value for normal or compressed mode. Additionally write the index value
to the same register (bit 2..0). Write DMA data to registers DWDRL and DWDRH (see
VHFWLRQ
page 74 and
VHFWLRQ
page 74) and the RMW mask to registers DMRL
and DMRH (see
VHFWLRQ
page 75 and
VHFWLRQ
for the OAM are needed when use of OAM is intended. Herefore setup the counter limits
for state transitions in the registers SCCONF0 and SCCONF1 (see
VHFWLRQ
and
VHFWLRQ
page 79).
3.
The SCAN mechanism is started by the following actions. Write respective settings to the
SCAN command register SCCONF3 (see
VHFWLRQ
by setting bit 0. This bit is reset as soon as the SCAN mechanism is started internally.
4.
The SCAN is finished when the start bit is reset and bit 0 of the SCAN status register is
equal to ’0’ (see
VHFWLRQ
page 81).
The registers in the SCAN block are write protected during the SCAN operation.
page 80) and the last LCI
page 81). Write the values
page 79 and
VHFWLRQ
page 77)
page 75). At last adjustments
page 78
page 80). The SCAN is started
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