
3;%(
Data Sheet
4-131
04.2000
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Also in normal operation the local controller checks all data collection entries, compares the
values with the given thresholds and if these are exceeded
Activates AIS/RDI insertion and
Informs network management
Optionally records of the e.g. last 15 minutes could be collected on-board for the last 24 hours.
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Events are unpredictable for the peripheral controller. These may be interrupts from the HW or
command messages received from the system controller .
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Such failures are e.g. line breaks or transmitter/receiver failure. They are detected by the PHY
device and usually signalled to the local controller by interrupt. If the failure is confirmed the local
controller
sets the corresponding PHY error bit in a AOP register
to signal the failure to the ATM layer. All ensuing actions as generation of VP-AIS or VC-AIS cells
in forward direction as well as the insertion of VP-RDI or VC-RDI cells in backward direction are
done automatically by the scan mechanism.
11
CRDIF2N
F5
2
17
Indication for a state transition from F5 RDI
failure state to F5 RDI normal state.
Indication for a state transition from F5 RDI
defect state to F5 RDI failure state.
Indication for a state transition from F5 AIS
failure state to F5 AIS normal state.
Indication for a state transition from F5 AIS
defect state to F5 AIS failure state.
10
CRDID2F
F5
2
16
9
CAISF2N
F5
2
15
8
CAISD2F
F5
2
14
7
6
5
4
3
2
1
0
’0’ always
’0’ always
CLOCFAI
CLOCDEF
CRDIFAI
CRDIDEF
CAISFAI
CAISDEF
-
-
F5
F5
F5
F5
F5
F5
-
-
1
1
1
1
1
1
-
-
5
4
3
2
1
0
F5 LOC failure state.
F5 LOC defect state.
F5 RDI failure state.
F5 RDI defect state.
F5 AIS failure state.
F5 AIS defect state.
1)
Refer to the external RAM (identical for up- and downstream RAM).
2)
For detailed explanation see section 3.9.1, page 98, section 3.9.2, page 104, section 3.9.3, page 110 and
section 3.9.4, page 116.
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