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| 型號(hào)： | PXB4350E |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | ICs for Communications |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 40/185頁 |
| 文件大小： | 2552K |
| 代理商： | PXB4350E |
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3;%(
Data Sheet
2-40
04.2000
)XQFWLRQDO'HVFULSWLRQ
The first BR cell is generated when the first FM cell for this PM flow has been received. This BR
cell carries valid data to initialize the BR data collection point, but no valid data for data
collection. Only the following BR cells contain valid data for data collection.
The PM function is split into three different parts:
PM generation
PM analysis and loop
PM data collection.
PM generation includes
Calculation of total user cell count for all cells and for high priority cells (CLP=0)
Calculation of a BIP-16 checksum over user cell payload
Generation of FM cells containing the calculated results.
The FM cells are coded as F4 or F5 automatically for VPCs and VCCs, respectively, end-end or
segment as specified. FM cell sequence number and CRC-10 checksum are also generated.
The blocksize can be selected between 2 and 65536. The optional time stamp of the FM cell is
not generated.
Forced OAM cell insertion is used for both up- and downstream FM cell insertion. During
insertion of FM cells the user cell stream is stored in the respective buffers (see
VHFWLRQ
PM analysis and loop include
Calculation of total user cell count for all cells and for high priority cells (CLP=0)
Extraction of FM cells
Appending of calculation results to the end of the cell
Conversion of the cell into a BR cell
Re-insertion of the BR cell in opposite direction.
PM analysis uses the same PM processor circuits as the generation process. In total 128 PM
processor circuits are shared by up- and downstream direction.
For PM data collection 128 circuits are provided, which are independent of the PM processor
circuits. Both PM and data collection processors have their respective entries in the internal PM/
data collection RAMs.
The assignment of PM and data collection processors to connections in up- or downstream
direction is arbitrary. VPCs and VCCs can be assigned by programming pointers in the F4 and
F5 entries, respectively (see
VHFWLRQ
page 121, and
VHFWLRQ
).
page 123).
([DPSOH
A typical PM scenario is shown in
ILJXUH
are involved, Node ’a’ where the VPC
a-b
is created and Node ’b’ where VPC
a-b
is terminated. In
backward direction the associated VPC
b-a
is created in Node ’b’ and terminated in Node ’a’.
Creation of a VPC allways occurs at an outgoing port of a node and termination at an incoming
port. Hence the Originating End Point (OEP) of VPC
a-b
is located in the downstream part of the
PXB 4340 AOP in Node a, and the Terminating End Point (TEP) of VPC
a-b
is located in the
upstream part of the PXB 4340 AOP in Node b. For VPC
b-a
the situation is mirrored according
to
ILJXUH
.
in case of VP end-to-end monitoring. Two nodes
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