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| 型號(hào)： | PXB4350E |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | ICs for Communications |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 73/185頁(yè) |
| 文件大?。?/td> | 2552K |
| 代理商： | PXB4350E |
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Data Sheet
3-73
04.2000
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The SCAN performs the OAM functions AIS, RDI and CC for all connections. It must be triggered
by the microprocessor in 500 ms intervals. The SCAN procedure goes through all requested
entries of the external connection memory, reads the data and writes back updated information.
E.g. the SCAN checks if user cells has been received, increments counters and accordingly
performs transitions in the AIS/RDI/CC state diagrams. Also AIS/RDI/CC cell insertion is done
by the scan. The SCAN starts with the lower LCI bound programmed by the user and ends at
the higher LCI bound. If for a connection a cell is to be inserted the SCAN halts the user cell
stream for one cell cycle. The user cells are buffered intermediately (see
ILJXUH
12).
A SCAN cycle of one LCI lasts 32 clock cycles like a cell access. It uses idle times, i.e. it is
initiated if no complete cell is available in the input UTOPIA buffer. Hence a certain number of
idle cell cycles is needed by the SCAN to do its work. The idle cell cycles can be calculated from
the difference between the sum of PHY payload rates and the maximum cell processing rate of
the PXB 4340 AOP.
7DEOH
shows some example values for SCAN period times as a function
of PHY payload rates. It can be seen that 673 Mbit/s is the highest possible aggregate PHY
payload rate if 16 K connections are used.
The SCAN periods in
7DEOH
are minimum values, as additional idle cycles occur if the PHYs
user cell rate is below 100%. A typical link load value is <100%. The spare bandwidth is used
for OAM cell insertion and microprocessor accesses to the external RAMs.
While the SCAN mechanism processes the entries of all connections the DMA function can be
activated. The read value of one specified Dword of each entry can be transferred to the
microprocessor via a 32-entry DMA buffer. The occupied DMA buffer is signalled to the
microprocessor via the MPDREQ pin. Also selected bits of the specified DMA entry can be
overwritten during the DMA process, e.g. to clear state transition flags.
With the Compressed DMA option a special Dword with a collection of state transition and status
flags is transferred to the DMA buffer during the scan. This option allows to check the status of
all connections rapidly.
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600 Mbit/s
1.415 Mcells/s
204 906 cycles/s
80 ms
625 Mbit/s
1.474 Mcells/s
145 943 cycles/s
112 ms
650 Mbit/s
1.533 Mcells/s
86 981 cycles/s
188 ms
673 Mbit/s
1.587 Mcells/s
32 768 cycles/s
500 ms
687 Mbit/s
1.620 Mcells/s
0
not possible
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