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| 型號(hào)： | PXB4350E |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | ICs for Communications |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 129/185頁(yè) |
| 文件大?。?/td> | 2552K |
| 代理商： | PXB4350E |
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Data Sheet
4-129
04.2000
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This command is issued by the microprocessor either on request from the system controller or
in the course of a activation/deactivation cell received for this connection. The following
parameters are needed:
LCI of the connection or LCI2 of the VP-pointer
Block size 128, 256, 512 or 1024
Mode select:
1) generate and collect data or
2) analyze and loop.
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6FDQ3URFHVV7ULJJHU
In fault free state the main task of the microprocessor is to trigger the scan function in 500 ms
intervals. This is done by setting one single bit in a register. An internal logic checks all requested
entries (from LCI min. to LCI max) of both up- and downstream external RAMs. According to the
actual state of the connection (AIS state, PHY failure, CC state etc.) and the programmed time-
out values the respective state transitions are performed automatically by the AOP. In addition
an interrupt bit is set if a state transition to or from failure state occurred. As long as no state
transition occurs nothing else has to be done by the microprocessor than to trigger the scan in
500 ms intervals.
In case of an interrupt the microprocessor must determine the connection which triggered the
(common) interrupt. For this purpose the compressed DMA function is enabled together with the
next scan, which transfers the status dword of all connections from both up- and downstream
external RAM to the microprocessor memory. The status dword contains:
VP/VC AIS/RDI/LOC defect/failure state
transition events between these states and fault-free state
error indication bits
direction bit.
The compressed DMA can be programmed to clear the transition event bits after read within the
same scan/DMA process (
VHH)LJXUH
).
The microprocessor is informed by the AOP about transitions to failure states and back to fault-
free states via interrupt. According to the standards transitions to defect states are not reported.
Scan and DMA completion is indicated by flags. With one 32-bit dword transferred per
connection and per direction, in total up to 32 K dwords are transferred to the microprocessor
memory. The dwords are stored in the designated RAM area with ascending LCI values from
lower to upper LCI limit. Upstream and downstream dword of a LCI are adjacent, but their order
is undetermined. The direction bit must be evaluated for each dword.
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