參數資料
型號： RG82870P2
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數據表參考
文件頁數： 13/157頁
文件大?。?/td> 1407K
代理商： RG82870P2
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
11
R
Terminology
MCH-M - The Mobile Memory Controller Hub-M component that contains the processor interface,
DRAM controller, and AGP interface. It communicates with the I/O controller hub (ICH3-M) and other
IO controller hubs over proprietary interconnect called the hub interface.
ICH3-M - The Mobile I/O Controller Hub 3-M component that contains the primary PCI interface, LPC
interface, USB, ATA-100, AC’97, and other IO functions. It communicates with the Intel
845MP/845MZ Chipset MCH-M over a proprietary interconnect called hub interface.
Host - This term is used synonymously with processor.
Core - The internal base logic in the MCH-M.
System Bus - Processor-to-MCH-M interface. The Enhanced Mode of the Scalable Bus is the P6 Bus
plus enhancements, consisting of source synchronous transfers for address and data, and system bus
interrupt delivery. The Mobile Intel Pentium 4 Processor-M implements a subset of Enhanced Mode.
Hub interface - The proprietary hub interconnect that ties the MCH-M to the ICH3-M. In this document
hub interface cycles originating from or destined for the primary PCI interface on the ICH3-M is
generally referred to as hub interface cycles.
Accelerated Graphics Port (AGP) - Refers to the AGP interface that is in the MCH-M. It supports
AGP 2.0 compliant components only with 1.5V signaling level. PIPE# and SBA addressing cycles and
their associated data phases are generally referred to as AGP transactions. FRAME# cycles over the AGP
bus are generally referred to as AGP/PCI transactions.
PCI_A - The physical PCI bus, driven directly by the ICH3-M component. It supports 5-V, 32-bit, 33-
MHz PCI 2.2 compliant components. Communication between PCI_A and MCH-M occurs over hub
interface. Note: Even though it is referred to as PCI_A it is not PCI Bus #0 from a configuration
standpoint.
Full Reset - A Full MCH-M Reset is defined in this document when RSTIN# is asserted.
System Bus - Synonymous with Host or Front Side Bus
GART - Graphics Aperture Re-map Table. This table contains the page re-map information used during
AGP aperture address translations.
GTLB - Graphics Translation Look-aside Buffer. A cache used to store frequently used GART entries.
UP – Uniprocessor
DBI – Dynamic Bus inversion
MSI – Message Signaled Interrupts. MSI’s allow a device to request interrupt service via a standard
Memory Write transaction instead of through a hardware signal.
IPI – Inter Processor Interrupt
Word – 16 bits = 2 bytes
Dword (DW) – Doubleword: 32bits = 4 bytes
相關PDF資料
PDF描述
RH5RE36AA-T1-FA 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3
RH5RE56AA-T1-FA 5.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3
RE5RE36AA-TZ-FC 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PBCY3
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相關代理商/技術參數
參數描述
RG82870P2 S L675 制造商:Intel 功能描述:Interface, Dual-Channel Ddr200 Memory Interface For Up To 3.2 Gb/S Memory Bandwidth
RG82870P2 S L6SU 制造商:Intel 功能描述:INTERFACE, DUAL-CHANNEL DDR200 MEMORY INTERFACE FOR UP TO 3.2 GB/S MEMORY BANDWIDTH
RG82870P2 SL6SU 制造商:Intel 功能描述:
RG-8B-96-110V 制造商:TRUMETER COMPANY INC 功能描述:Power Factor Controller
RG-8BS-96-110V 制造商:TRUMETER COMPANY INC 功能描述:Power Factor Controller
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