參數(shù)資料
型號： RG82870P2
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 68/157頁
文件大小： 1407K
代理商： RG82870P2
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
18
Datasheet
250687-002
R
1.4.
AGP Interface
A single AGP component or connector (not both) is supported by the Intel 845MP/845MZ Chipset
MCH-M AGP interface. The AGP buffers operate only in 1.5-V mode. They are not 3.3-V safe.
The AGP interface supports 1x/2x/4x AGP signaling and 2x/4x Fast Writes. AGP semantic cycles to
DRAM are not snooped on the host bus. PCI semantic cycles to DRAM are snooped on the host bus. The
MCH-M supports PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously. Either the
PIPE# or the SBA[7:0] mechanism must be selected during system initialization. Both upstream and
downstream addressing is limited to 32 bits for AGP and AGP/PCI transactions. The MCH-M contains a
32-deep AGP request queue. High priority accesses are supported. All accesses from the AGP/PCI
interface that fall within the Graphics Aperture address range pass through an address translation
mechanism with a fully associative 20 entry TLB. Accesses between AGP and hub interface are limited
to memory writes originating from the hub interface destined for AGP. The AGP interface is clocked
from a dedicated 66MHz clock (66IN). The AGP-to-host/core interface is asynchronous.
Consult the latest AGP Busy and Stop Protocol Specification for more information.
1.5.
Hub Interface
The 8-bit hub interface connects the MCH-M to the ICH3-M. All communication between the MCH-M
and the ICH3-M occurs over the hub interface. The hub interface runs at 66 MHz/266 MB/s. Aside from
the obvious traffic types, the following communication also occur over hub interface:
Interrupt related messages
Power management events as messages
SMI, SCI, and SERR error indication messages
It is assumed that the hub interface is always connected to an ICH3-M. This is a proprietary interconnect
between the MCH-M and the ICH3-M.
1.6.
MCH-M Clocking
The MCH-M has the following clock input pins:
Differential BCLK[1:0] for the host interface
66-MHz clock input for the AGP and hub interface
Clock Synthesizer chip(s) are responsible for generating the system Host clocks, AGP and hub interface
clocks, PCI clocks, and DRAM clocks. The Host target speed is 400 MT/s. The MCH-M does not
require any relationship between the HCLKIN host clock and the 66-MHz clock generated for AGP and
hub interface; they are totally asynchronous from each other. The AGP and hub interface runs at a
constant 66-MHz base frequency. The hub interface runs at 4x, while AGP transfers may be 1x, 2x, or
4x.
The following tables indicate the frequency ratios between the various interfaces that the MCH-M
supports.
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相關代理商/技術參數(shù)
參數(shù)描述
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RG82870P2 SL6SU 制造商:Intel 功能描述:
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