參數(shù)資料
型號(hào): RG82870P2
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù): 82/157頁(yè)
文件大?。?/td> 1407K
代理商: RG82870P2
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Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
30
Datasheet
250687-002
R
2.5.
Clocks, Reset, and Miscellaneous
Table 12. Clocks, Reset, and Miscellaneous Descriptions
Signal Name
Type
Description
BCLK /
BCLK#
I
CMOS
Differential Host Clock In: These pins receive a differential host clock from the
external clock synthesizer. This clock is used by all of the MCH-M logic that is in
the Host clock domain.
66IN
I
CMOS
66-MHz Clock In: This pin receives a 66-MHz clock from the clock synthesizer.
This clock is used by AGP/PCI and hub interface clock domains.
Note: That this clock input is 3.3-V tolerant.
SCK[5:0]
O
CMOS
SDRAM Differential Clock (DDR): These signals deliver a source synchronous
clock to
the SO-DIMMs. There are three per SO-DIMM.
SCK#[5:0]
O
CMOS
SDRAM Inverted Differential Clock (DDR): These signals are the complement to
the SCK[5:0] signals. There are three per
SO-DIMM.
RSTIN#
I
CMOS
Reset In: When asserted this signal will asynchronously reset the MCH-M logic.
This signal is connected to the PCIRST# output of the ICH3-M. All AGP/PCI output
and bi-directional signals will also tri-state compliant to PCI Rev 2.0 and 2.1
specifications.
Note: That this input needs to be 3.3-V tolerant.
TESTIN#
I
CMOS
Test Input: This pin is used for manufacturing and board level test purposes.
Note: This signal has an internal pullup resistor.
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