參數(shù)資料
型號: RG82870P2
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 83/157頁
文件大?。?/td> 1407K
代理商: RG82870P2
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
31
R
2.6.
Voltage References, PLL Power
Table 13. Voltage Reference Descriptions
Signal Name
Type
Description
HVREF
Ref
Host Reference Voltage. Reference voltage input for the Data, Address, and
Common clock signals of the Host AGTL+ interface
SDREF
Ref
DDR Reference Voltage: Reference voltage input for DQ, DQS, & RCVENIN#.
HI
_REF
Ref
Hub Interface Reference: Reference voltage input for the hub interface.
AGPREF
Ref
AGP Reference: Reference voltage input for the AGP interface.
HLRCOMP
I/O
CMOS
Compensation for hub interface: This signal is used to calibrate the hub
interface I/O buffers.
GRCOMP
I/O
CMOS
Compensation for AGP: This signal is used to calibrate AGP buffers.
HRCOMP[1:0]
I/O
CMOS
Compensation for Host: This signal is used to calibrate the Host AGTL+ I/O
buffers.
HSWNG[1:0]
I
CMOS
Host Reference Voltage: Reference voltage input for the compensation logic.
SMRCOMP
I/O
CMOS
System Memory RCOMP
VCC1_5
The 1.5 V Power input pins
VCC1_8
The 1.8 V Power input pins
VCCSM
The SDRAM Power input pins. 2.5 V for DDR.
VCCA[1:0]
PLL power input pins.
VTT
The AGTL+ bus termination voltage inputs
VSS
GROUND
VSSA[1:0]
PLL Ground
2.7.
Pin State Table
This section describes the expected states of the MCH-M I/O buffers. These tables only refer to the
contributions on the interface from the MCH-M and do NOT reflect any external influence (such as
external pullup/pulldown resistors or external drivers).
Legend :
Term H/L:Normal termination devices are turned on high/low
Pwrdn:
Power down
H/L:
Strong Drive low
Tri/High-Z:
High Impedance
IN:
Input buffer Enabled
PU, PD/PL:
Weak internal pull-up, Weak internal pull down
(Strap):
Strap input sampled during assertion or on the deassertion edge of RSTIN#
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