- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄98076 > SAK-TC1765T-L40EB (INFINEON TECHNOLOGIES AG) 32-BIT, MROM, 40 MHz, MICROCONTROLLER, PBGA260 PDF資料下載
參數(shù)資料
| 型號(hào)： | SAK-TC1765T-L40EB |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 40 MHz, MICROCONTROLLER, PBGA260 |
| 封裝： | PLASTIC, LBGA-260 |
| 文件頁(yè)數(shù)： | 10/88頁(yè) |
| 文件大?。?/td> | 1274K |
| 代理商： | SAK-TC1765T-L40EB |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)當(dāng)前第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)
TC1765
Data Sheet
14
V1.2, 2002-12
Preliminary
TDO
R12
O
JTAG Module Serial Data Output3)
TMS8)
V15
I
JTAG Module State Machine Control Input
OCDSE8)
R11
I
OCDS Enable Input
A low level on this pin during power-on reset (PORST =0)
enables the on-chip debug support (OCDS). In addition, the
level of this pin during power-on reset determines the boot
configuration.
BRKIN8)
U15
I
OCDS Break Input
A low level on this pin causes a break in the chip’s execution
when the OCDS is enabled. In addition, the level of this pin
during power-on reset determines the boot configuration.
BRKOUT
T12
O
OCDS Break Output3)
A low level on this pin indicates that a programmable OCDS
event has occurred.
NMI8)
U17
I
Non-Maskable Interrupt Input
A high-to-low transition on this pin causes an NMI-Trap
request to the CPU.
HDRST8)
P18
I/O
Hardware Reset Input / Reset Indication Output6)
Assertion of this open-drain bidirectional pin causes a
synchronous reset of the chip through external circuitry.
The internal reset circuitry drives this pin in response to a
power-on, hardware, watchdog and power-down wake-up
reset for a specific period of time. For a software reset, it is
programmable whether this pin is activated or not.
PORST
T17
I
Power-on Reset Input
A low level on PORST causes an asynchronous reset of the
entire chip. During power-up of the TC1765, this pin must be
held active (low).
BYPASS
N17
I
PLL Bypass Control Input
This pin is sampled during power-on reset (PORST = 0). If
BYPASS is at high level, direct drive mode operation of the
clock circuitry is selected and the PLL is bypassed.
Table 1
Pin Definitions and Functions (cont’d)
Symbol
Pin
In
Out
Functions
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAK-TC1767-256F133HL | 32-BIT, FLASH, 133 MHz, RISC MICROCONTROLLER, PQFP176 |
| SAK-TC1782-320F180HL | 32-BIT, FLASH, 180 MHz, RISC MICROCONTROLLER, PQFP176 |
| SAK-XC164CS-32F40F | 16-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP100 |
| SAK-XC164CS-32F20F | 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQFP100 |
| SAK-XC2267M-104F80LAA | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAK-TC1766-192F80HL | 制造商:Infineon Technologies AG 功能描述:Tricore,32 bit,1.5MB Flash,80MHz,USB |
| SAK-TC1766-192F80HL BD | 功能描述:32位微控制器 - MCU 32BIT SNGL CHIP 3.3V 80MHz Flash RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| SAK-TC1766-192F80HL BDTR | 制造商:Infineon Technologies AG 功能描述: |
| SAKTC1766192F80HLBBX | 制造商:Infineon Technologies AG 功能描述:MCU 32-bit TC17xx TriCore RISC 1536KB Flash 1.5V/3.3V 176-Pin LQFP |
| SAK-TC1766-192F80HLBD | 制造商:Infineon Technologies AG 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。