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| 型號(hào)： | SAK-TC1765T-L40EB |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 40 MHz, MICROCONTROLLER, PBGA260 |
| 封裝： | PLASTIC, LBGA-260 |
| 文件頁(yè)數(shù)： | 18/88頁(yè) |
| 文件大?。?/td> | 1274K |
| 代理商： | SAK-TC1765T-L40EB |
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TC1765
Data Sheet
21
V1.2, 2002-12
Preliminary
High-Speed Synchronous Serial Interfaces
Figure 6 shows a global view of the functional blocks of the two High-Speed
Synchronous Serial interfaces SSC0 and SSC1.
Figure 6
General Block Diagram of the SSC Interfaces
Each of the SSC modules has three I/O lines, located at Port 0 and Port 5. Each of the
SSC modules is further supplied by separate clock control, interrupt control, address
decoding, and port control logic.
The SSC supports full-duplex and half-duplex serial synchronous communication up to
20 Mbit/s (@ 40 MHz module clock) with receive and transmit FIFO support. The serial
clock signal can be generated by the SSC itself (master mode) or can be received from
an external master (slave mode). Data width, shift direction, clock polarity, and phase are
programmable. This allows communication with SPI-compatible devices. Transmission
M C B 05051
Cloc k
C ontro l
Add res s
Dec od er
Inte rrup t
C ontro l
f
SS C 0
SS C0
M odule
(K e rne l)
Cloc k
C ontro l
Add res s
Dec od er
Inte rrup t
C ontro l
f
SSC 1
SS C1
M odule
(K e rne l)
RX D
TX D
Ma
s
te
r
RX D
TX D
Sl
a
v
e
Slav e
Ma ste r
SCL
K
RX D
TX D
Ma
s
te
r
RX D
TX D
Sl
a
v
e
Slav e
Ma ste r
SCL
K
Port 0
Co ntrol
P0.1 0 /
MR S T 0
P0.1 1 /
MT S R 0
P 0.9 /
SC L K 0
Port 5
Co ntrol
P 5.4 /
MT S R 1
P 5.3 /
MR S T 1
P 5.2 /
SC L K 1
EIR
RIR
To D M A
EIR
TIR
RIR
To D M A
TIR
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