參數(shù)資料
型號(hào)： SAK-TC1765T-L40EB
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 40 MHz, MICROCONTROLLER, PBGA260
封裝： PLASTIC, LBGA-260
文件頁數(shù)： 39/88頁
文件大小： 1274K
代理商： SAK-TC1765T-L40EB
TC1765
Data Sheet
40
V1.2, 2002-12
Preliminary
DMA Controller
The Direct Memory Access (DMA) Controller executes DMA transactions from a source
address location to a destination address location, without intervention of the CPU. One
DMA transaction is controlled by one DMA channel.
Each of the two blocks in the DMA controller, block 0 and block 1 (see Figure 12),
provides four DMA channels with sixteen DMA request inputs. The request assignment
unit in each sub-block assigns one DMA request input to each DMA channel. The control
unit includes a third request unit dedicated especially for request control through I/O
pins. This unit connects two of eight request inputs with two request outputs which can
be then wired externally of the DMA controller module to the request inputs of the two
DMA controller blocks. Request assignment unit 2 evaluates pulses or levels by its edge
detect and level select logic.
Features:
8 independent DMA channels (4 per DMA block)
– 4 DMA selectable request inputs per DMA channel
– Fixed priority of DMA channels within a DMA block
– Software and hardware DMA request generation
Support of FPI Bus to FPI Bus DMA transactions
Individually programmable operation modes for each DMA channel
– Single mode: stops and disables DMA channel after a predefined number of DMA
transfers
– Continuous mode: DMA channel remains enabled after a predefined number of
DMA transfers; DMA transaction can be repeated
Full 32-bit addressing capability of each DMA channel
– 4 Gbyte address range
– Source and destination transfer individually programmable in steps from 0 to
255 bytes
– Support of circular buffer addressing mode
Programmable data width of a DMA transaction: 8-bit, 16-bit, or 32-bit
Register set for each DMA channel
– Source and destination start address register
– Source and destination end address register
– Channel control and status register
– Offset and transfer count register
Bus bandwidth allocation
Flexible interrupt generation
Figure 12 shows the TC1765 specific implementation details and interconnections of
the DMA module. The DMA module is further supplied by a separate clock control,
address decoding, interrupt control, port control logic.
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