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參數(shù)資料
| 型號： | SAK-TC1765T-L40EB |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 40 MHz, MICROCONTROLLER, PBGA260 |
| 封裝： | PLASTIC, LBGA-260 |
| 文件頁數(shù)： | 20/88頁 |
| 文件大?。?/td> | 1274K |
| 代理商： | SAK-TC1765T-L40EB |
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TC1765
Data Sheet
23
V1.2, 2002-12
Preliminary
TwinCAN Interface
Figure 7 shows a global view of the functional blocks of the TwinCAN module.
Figure 7
General Block Diagram of the TwinCAN Module
The TwinCAN module has four I/O lines located at Port 0. The TwinCAN module is
further supplied by a clock control, interrupt control, address decoding, and port control
logic.
The TwinCAN module contains two Full-CAN nodes operating independently or
exchanging data and remote frames via a gateway function. Transmission and reception
of CAN frames are handled in accordance to CAN specification V2.0 part B (active).
Each of the two Full-CAN nodes can receive and transmit standard frames with 11-bit
identifiers as well as with extended frames with 29-bit identifiers.
Both CAN nodes share the TwinCAN module’s resources to optimize the CAN bus traffic
handling and to minimize the CPU load. The flexible combination of Full-CAN
functionality and the FIFO architecture reduces the efforts to fulfill the real-time
requirements of complex embedded control applications. Improved CAN bus monitoring
functionality as well as the increased number of message objects permit precise and
convenient CAN bus traffic handling.
Depending on the application, each of the thirty-two message objects can be individually
assigned to one of the two CAN nodes. Gateway functionality allows automatic data
exchange between two separate CAN bus systems, which decreases CPU load and
improves the real time behavior of the entire system.
Tw in C A N M odule K e rnel
Me ssa g e
Bu ffe rs
M C B 05059
Clo ck
C ontro l
Ad d re ss
D e code r
In te rrupt
C ontro l
SR 1
SR 2
f
CA N
SR 3
SR 0
Po rt
Co n tro l
P 0 .13 /
TX D C A N 0
P 0 .12 /
RX D C A N 0
SR 7
SR 6
SR 5
P 0 .15 /
TX D C A N 1
P 0 .14 /
RX D C A N 1
B itstre a m
P rocesso r
SR 4
T X DC0
RX DC0
T X DC1
RX DC1
E rro r
H a n d lin g
C ontro l
Tim ing
Co n tro l
In te rrupt
C ontro l
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