參數(shù)資料
型號(hào)： SAK-TC1765T-L40EB
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 40 MHz, MICROCONTROLLER, PBGA260
封裝： PLASTIC, LBGA-260
文件頁(yè)數(shù)： 17/88頁(yè)
文件大?。?/td> 1274K
代理商： SAK-TC1765T-L40EB
TC1765
Data Sheet
20
V1.2, 2002-12
Preliminary
Each ASC module, ASC0 and ASC1, communicates with the external world via two I/O
lines. The RXD line is the receive data input signal (in Synchronous Mode also output).
TXD is the transmit output signal. Clock control, address decoding, and interrupt service
request control are managed outside the ASC module kernel.
The Asynchronous/Synchronous Serial Interfaces provide serial communication
between the TC1765 and other microcontrollers, microprocessors, or external
peripherals.
The
ASC
supports
full-duplex
asynchronous
communication
and
half-duplex
synchronous communication. In Synchronous Mode, data is transmitted or received
synchronous to a shift clock which is generated by the ASC internally. In Asynchronous
Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be
selected. Parity, framing, and overrun error detection are provided to increase the
reliability of data transfers. Transmission and reception of data are double-buffered. For
multiprocessor communication, a mechanism is included to distinguish address bytes
from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator
provides the ASC with a separate serial clock signal that can be very accurately adjusted
by a prescaler implemented as a fractional divider.
Features:
Full-duplex asynchronous operating modes
– 8-bit or 9-bit data frames, LSB first
– Parity bit generation/checking
– One or two stop bits
– Baud rate from 2.5 Mbit/s to 0.6 Bit/s (@ 40 MHz clock)
– Multiprocessor mode for automatic address/data byte detection
– Loop-back capability
Half-duplex 8-bit synchronous operating mode
– Baud rate from 5 Mbit/s to 406.9 Bit/s (@ 40 MHz clock)
Double buffered transmitter/receiver
Interrupt generation
– On a transmitter buffer empty condition
– On a transmit last bit of a frame condition
– On a receiver buffer full condition
– On an error condition (frame, parity, overrun error)
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