參數(shù)資料
型號(hào)： SAK-TC1765T-L40EB
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 40 MHz, MICROCONTROLLER, PBGA260
封裝： PLASTIC, LBGA-260
文件頁數(shù)： 76/88頁
文件大?。?/td> 1274K
代理商： SAK-TC1765T-L40EB
TC1765
Data Sheet
74
V1.2, 2002-12
Preliminary
PLL Parameters
Note: All PLL characteristics defined on this and the next page are guaranteed by design
characterization.
VSS = 0 V; VDD = 2.30 to 2.75 V; TA = -40 °C to +125 °C;
Phase Locked Loop Operation
When PLL operation is enabled and configured (see Figure 16 and Page 51), the PLL
clock
fVCO (and with it the system clock fSYS) is constantly adjusted to the selected
frequency. The relation between
fVCO and fSYS is defined by: fVCO =K × fSYS. The PLL
causes a jitter of
fSYS and CPUCLK/ECOUT, which is directly derived from fSYS and
which has its frequency.
The following two formulas define the (absolute) approximate maximum value of jitter
DN
in ns dependent on the K-factor, the system clock frequency
fSYS in MHz, and the
number
P of consecutive fSYS periods.
[1]
[2]
With rising number
P of clock cycles the maximum jitter increases linearly up to a value
of
P that is defined by the K-factor of the PLL. Beyond this value of P the maximum
accumulated jitter remains at a constant value. Further, a lower system clock frequency
fSYS results in a higher maximum jitter.
gives
an
example
for
typical
jitter
curves
with
K =4 @40MHz,
K = 6 @33 MHz, and K = 8@20/25 MHz.
Parameter
Symbol
Limit Values
Unit
min.
max.
Accumulated jitter
DN
–
VCO frequency range
fVCO
150
200
MHz
PLL base frequency
fPLLBASE
40
130
MHz
PLL lock-in time
tL
–
200
s
for
P <
23.5
K
DN [ns] = ±
3.9
fSYS [MHz]
× P + 1.2
for
P >
23.5
K
DN [ns] = ±
91.7
fSYS [MHz] × K
+ 1.2
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