參數(shù)資料
型號: SAK-TC1765T-L40EB
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, MROM, 40 MHz, MICROCONTROLLER, PBGA260
封裝: PLASTIC, LBGA-260
文件頁數(shù): 41/88頁
文件大?。?/td> 1274K
代理商: SAK-TC1765T-L40EB
TC1765
Data Sheet
42
V1.2, 2002-12
Preliminary
System Timer
The TC1765’s System Timer (STM) is designed for global system timing applications
requiring both high precision and long range. The STM has the following features:
Free-running 56-bit counter
All 56 bits can be read synchronously
Different 32-bit portions of the 56-bit counter can be read synchronously
Driven by clock
fSTM (identical to the system clock fSYS)
Counting starts automatically after a reset operation (except a hardware reset)
The STM is an upward counter, running with the system clock frequency (
fSTM = fSYS).
It is enabled per default after reset, and immediately starts counting up. Other than via
reset, it is no possible to affect the contents of the timer during normal operation of the
application, it can only be read, but not written to. Depending on the implementation of
the clock control of the STM, the timer can optionally be disabled or suspended for
power-saving and debugging purposes via a clock control register.
The maximum clock period is 256
× 1 / f
STM. At fSTM = 40 MHz, for example, the STM
counts 57.1 years before overflowing. Thus, it is capable of continuously timing the entire
expected product life-time of a system without overflowing.
Figure 13
Block Diagram of the System Timer Module
STM M odule
00
H
CA P
TIM 6
TIM 5
TIM 4
TIM 3
TIM 2
TIM 1
TIM 0
00
H
55
47
39
31
23
15
7
56 -B it S y ste m Tim e r
Add res s
D ecoder
Clo ck
Co ntro l
E nable /
Disa ble
PO R S T
f
ST M
M C A 04795
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