9t
參數(shù)資料
型號： SPC5634MF1MMG80
廠商： Freescale Semiconductor
文件頁數(shù)： 116/122頁
文件大小： 0K
描述： IC MCU FLASH 1.5M 94K 208-PBGA
標準包裝： 90
系列： MPC56xx Qorivva
核心處理器： e200z3
芯體尺寸： 32-位
速度： 80MHz
連通性： CAN，EBI/EMI，LIN，SCI，SPI，UART/USART
外圍設備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 114
程序存儲器容量： 1.5MB（1.5M x 8）
程序存儲器類型： 閃存
RAM 容量： 94K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 34x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 150°C
封裝/外殼： 208-BGA
包裝： 托盤
Electrical characteristics
MPC5634M Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
93
Figure 13. Nexus output timing
9tTCYC
CC
D TCK Cycle Time
46,7
—tCYC
9a
tTCYC
CC
D Absolute Minimum TCK Cycle Time
1008
—ns
10
tTDC
CC
D TCK Duty Cycle
40
60
%
11
tNTDIS
CC
D TDI Data Setup Time
5
—
ns
12
tNTDIH
CC
D TDI Data Hold Time
25
—
ns
13
tNTMSS
CC
D TMS Data Setup Time
5
—
ns
14
tNTMSH
CC
D TMS Data Hold Time
25
—
ns
15
tJOV
CC
D TCK Low to TDO Data Valid
10
20
ns
1 All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing
specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.25 V with multi-voltage pads programmed to Low-Swing
mode, TA = TL to TH, and CL = 30 pF with DSC = 0b10.
2 Achieving the absolute minimum MCKO cycle time may require setting the MCKO divider to more than its minimum
setting (NPC_PCR[MCKO_DIV] depending on the actual system frequency being used.
3 This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the
Absolute minimum MCKO period specification.
4 This may require setting the MCKO divider to more than its minimum setting (NPC_PCR[MCKO_DIV]) depending
on the actual system frequency being used.
5 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
6 Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that
is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system
frequency being used.
7 This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the
Absolute minimum TCK period specification.
8 This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability
of the design (system frequency / 4) depending on the actual system frequency being used.
Table 37. Nexus debug port timing1 (continued)
#
Symbol
C
Characteristic
Min. Value Max. Value
Unit
1
2
4
6
MCKO
MDO
MSEO
EVTO
Output Data Valid
3
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