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參數(shù)資料
| 型號(hào)： | SPC5634MF1MMG80 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 68/122頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 1.5M 94K 208-PBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | MPC56xx Qorivva |
| 核心處理器： | e200z3 |
| 芯體尺寸： | 32-位 |
| 速度： | 80MHz |
| 連通性： | CAN，EBI/EMI，LIN，SCI，SPI，UART/USART |
| 外圍設(shè)備： | DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 114 |
| 程序存儲(chǔ)器容量： | 1.5MB（1.5M x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 94K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 34x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 150°C |
| 封裝/外殼： | 208-BGA |
| 包裝： | 托盤 |
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MPC5634M Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
5
– Allows selection of interrupt requests between external pins and DSPI
Error correction status module (ECSM)
— Configurable error-correcting codes (ECC) reporting
— Single-bit error correction reporting
On-chip flash memory
— Up to 1.5 MB flash memory, accessed via a 64-bit wide bus interface
— 16 KB shadow block
— Fetch Accelerator
– Provide single cycle flash access at 80 MHz
– Quadruple 128-bit wide prefetch/burst buffers
– Prefetch buffers can be configured to prefetch code or data or both
— Censorship protection scheme to prevent flash content visibility
— Flash divided into two independent arrays, allowing reading from one array while erasing/programming the other
array (used for EEPROM emulation)
— Memory block:
– For MPC5634M: 18 blocks (4
16 KB, 2 32 KB, 2 64 KB, 10 128 KB)
– For MPC5633M: 14 blocks (4
16 KB, 2 32 KB, 2 64 KB, 6 128 KB)
– For MPC5632M: 12 blocks (4
16 KB, 2 32 KB, 2 64 KB, 4 128 KB)
— Hardware programming state machine
On-chip static RAM
— For MPC5634M: 94 KB general purpose RAM of which 32 KB are on standby power supply
— For MPC5633M: 64 KB general purpose RAM of which 32 KB are on standby power supply
— For MPC5632M: 48 KB general purpose RAM of which 24 KB are on standby power supply
Boot assist module (BAM)
— Enables and manages the transition of MCU from reset to user code execution in the following configurations:
– Execution from internal flash memory
– Execution from external memory on the calibration bus
– Download and execution of code via FlexCAN or eSCI
Periodic interrupt timer (PIT)
— 32-bit wide down counter with automatic reload
— Four channels clocked by system clock
— One channel clocked by crystal clock
— Each channel can produce periodic software interrupt
— Each channel can produce periodic triggers for eQADC queue triggering
— One channel out of the five can be used as wake-up timer to wake device from low power stop mode
System timer module (STM)
— 32-bit up counter with 8-bit prescaler
— Clocked from system clock
— Four-channel timer compare hardware
— Each channel can generate a unique interrupt request
— Designed to address AUTOSAR task monitor function
Software watchdog timer (SWT)
— 32-bit timer
— Clock by system clock or crystal clock
— Can generate either system reset or non-maskable interrupt followed by system reset
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